Design And Simulation Of An Intelligent Adaptive Arbiter For Maximum Cpu Usage Of Multicore Processors

The recent technology in the world of microprocessor is blended with complex chips that incorporate multiple processors dedicated for specific computational needs. Therefore, in any shared memory system, an arbitration technique plays an important role to allocate access to the shared resources. The major challenge dealt in the proposed research is the achievement of maximum CPU utilization by exploiting its multiple cores with moderate bus bandwidth allocation and low system latency. In order to tackle the aforesaid problems, an intelligent adaptive arbitration technique has been proposed for the masters designed according to the traffic behaviour of the data flow. The proposed intelligent adaptive arbitration technique is implemented using STREAM, which is a synthetic benchmark program that measures computational rate and sustainable memory bandwidth. In terms of performance analysis, the proposed arbitration technique has been compared with the recent arbitration technique, such as adaptive arbitration technique, dynamic lottery bus arbitration, round robin arbitration and static fixed priority arbitration. To enhance the CPU utilization and bandwidth optimization, the proposed arbitration technique has been modelled using SystemC and OpenMP threads using the method of parallel programming to enable multi-core computing. Some recent arbitration technique achieves fair bus bandwidth allocation up to some extent but fails to achieve maximum CPU utilization, as the processor spends 95-96 % of their time idle and waits for cache misses to be satisfied. The proposed arbitration technique is a strong case in favour of maximum CPU usage and bandwidth optimization, as it consumes the processor cores up to 74% and also reduces the bandwidth fluctuation as well as latency