Adaptive proportional-integral-derivative controller on field programmable gate array

Proportional-Integral-Derivative (PID) controllers tuned with heuristic tuning methods such as Ziegler-Nichols method are not completely capable to perform high precision control, typically due to large overshoots and poor load regulation. Any changes to the tunable PID parameters we done accordingly offline. Current Field Programmable Gate Array (FPGA) based platform can be used as a high-precision controller implementation. Using FPGA for high precision control offer good resource utilization, power consumption, programmability, cost, and more importantly, it can support parallel controllers. With the improvement of FPGA devices that sometime mirror the performance of the general purpose processor, more complex PID design such as adaptive PID can be implemented. Adaptive PID controller can adjust its own parameters and is able to simultaneously support multiple applications at once. The objective of this project is to design adaptive PID controller on FPGA and analyze the performance of it adaptive or self-tuning capabilities when reference and error signal vary. Another objective is to minimize the instability and reducing the overshoot, undershoot, settling time and ringing. The Altera Quartus and Altera ModelSim environments are used to model the adaptive PID using Verilog Hardware Description Language through Register Transfer Level modeling methodology. These tools are also used for simulating the controller and evaluating non-functional performance characterization.The overall adaptive PID result outperforms the conventional PID and offer slight improvement on noise injection test case