[[alternative]]使用混合數字系統之FPGA算術表現效能探討

碩士[[abstract]]本論文旨在探討將智慧型控制器透過混合數字系統之硬體架構實現於FPGA平台，並探討算術表示對於控制器計算效能的影響，同時套用TS-CMAC控制器模擬與實現；目的是透過Altera SOPC與NIOS II處理器的使用者指令集實現32位元混合數字系統處理器，並應用於TS-CMAC作為算術運算。其中，控制器的計算性能優劣取決於算術表示；然而，控制器實作上必須考量到所需要花費的FPGA邏輯元件成本，以及數字精度的影響，以上因素均會影響控整器整體效能之呈現；因此，本論文所提出的混合數字系統硬體化系統架構旨在解決以上問題。硬體化系統架構有以下三個優點： i) 低花費的FPGA邏輯元件； ii) 高運算效能； iii) 高精度的算術運算。經由實驗結果得知，透過混合數字系統能有效提升TS-CMAC的算術運算速度，同時在設計算術硬體上減少佔用面積並保有高數字精確度，達到TS-CMAC在控制上之準確性。[[abstract]]In this paper, we developed a hardware intelligent controller, such as TS-CMAC, implemented on a field programmable gate array (FPGA) platform. We also discuss the impact of arithmetic representation on computing performance of controller. In addition, we implemented a 32-bit hybrid number system processor for TS-CMAC arithmetic operations. However, arithmetic representations for intelligent controller is dependent on computing performance. The tradeoff between precision and representation along with FPGA logic element costs requirements are considered. Therefore, our hardware system architecture seek to fill the gap between why. We proposed hybrid number system for our controller arithmetic representation. The hardware system architecture has advantages: i) low costs of hardware logic element; ii) high computing performance; iii) high accuracy of arithmetic operation. According to experimental results, TS-CMAC arithmetic operation speed can be increased effectively by hybrid number system which can not only reduce area occupied of hardware but also maintain high precision in arithmetic hardware design, and thus enhance TS-CMAC accuracy in intelligent control .[[tableofcontents]]Table of Contents Abstract in Chinese I Abstract in English II Table of Contents III List of Figures VI List of Tables VIII 1 INTRODUCTION 1 1.1 Research Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Problem Formulation and Motivations . . . . . . . . . . . . . . . . . . 4 1.4 Organization of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 HYBRID NUMBER SYSTEM 7 2.1 Floating-Point Number System . . . . . . . . . . . . . . . . . . . . . . 8 2.1.1 Floating-Point Arithmetic Overview . . . . . . . . . . . . . . . . 8 2.1.2 Multiplication Algorithms . . . . . . . . . . . . . . . . . . . . . 11 2.1.3 Addition and Subtraction Algorithms . . . . . . . . . . . . . . . 14 2.1.4 Division Algorithms . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 Logarithmic Number System . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.1 Logarithmic Arithmetic Overview . . . . . . . . . . . . . . . . . 20 2.2.2 Multiplication and Division Algorithms . . . . . . . . . . . . . . 22 2.2.3 Addition and Subtraction Algorithms . . . . . . . . . . . . . . . 24 2.2.4 Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3 Conversion Algorithms of Format . . . . . . . . . . . . . . . . . . . . . 28 2.3.1 Design of Logarithm to Floating-Point . . . . . . . . . . . . . . 28 2.3.2 Design of Floating-Point to Logarithm . . . . . . . . . . . . . . 31 2.3.3 The Error of Conversion Algorithm . . . . . . . . . . . . . . . . 32 2.4 Exponential Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4.1 Exponential Algorithm . . . . . . . . . . . . . . . . . . . . . . . 33 3 OVERALL SYSTEM ARCHITECTURE AND ITS DESIGN 35 3.1 NIOS II Software Development Environment . . . . . . . . . . . . . . . 35 3.2 Altera SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.3 Custom Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.1 Custom Instructions of Arithmetic Operation . . . . . . . . . . 38 3.4 Takagi-Sugeno Fuzzy Cerebellar Model Articulation Controller . . . . . 40 3.4.1 Cerebellar Model Articulation Controller . . . . . . . . . . . . . 40 3.4.2 Takagi-Sugeno Fuzzy Theory . . . . . . . . . . . . . . . . . . . . 42 3.4.3 CMAC with T-S fuzzy model . . . . . . . . . . . . . . . . . . . 43 3.5 Overall System Structure of TS-CMAC . . . . . . . . . . . . . . . . . 47 3.6 Overall System Architecture . . . . . . . . . . . . . . . . . . . . . . . . 47 4 VERIFICATION AND EXPERIMENTAL RESULTS 49 4.1 Hardware Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.2 Hardware Costs and Experimental Results . . . . . . . . . . . . . . . . 52 4.2.1 Hardware Consumption of Logic Element . . . . . . . . . . . . . 52 4.2.2 Delay Time and Clock Cycle . . . . . . . . . . . . . . . . . . . . 54 5 CONCLUSIONS AND FUTURE OUTLOOK 57 5.1 Research Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2 Future Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Reference Materials 59 List of Figures 2.1 Hybrid number system architecture . . . . . . . . . . . . . . . . . . . . 7 2.2 IEEE 754 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 FLP representable number range diagram . . . . . . . . . . . . . . . . 10 2.4 FLP multiplication flow chart . . . . . . . . . . . . . . . . . . . . . . . 12 2.5 Structure of FLP multiplication . . . . . . . . . . . . . . . . . . . . . . 13 2.6 FLP addition and subtraction flow chart . . . . . . . . . . . . . . . . . 15 2.7 Structure of FLP addition . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.8 Structure of FLP subtraction . . . . . . . . . . . . . . . . . . . . . . . 17 2.9 Structure of FLP division . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.10 32-bit single precision LNS format . . . . . . . . . . . . . . . . . . . . . 20 2.11 Structure of LNS multiplication . . . . . . . . . . . . . . . . . . . . . . 23 2.12 Structure of LNS division . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.13 LNS addition and subtraction of f (k) . . . . . . . . . . . . . . . . . . . 26 2.14 Structure of LNS addition and subtraction . . . . . . . . . . . . . . . . 27 2.15 The hardware architecture of LNS-to-FLP conversion . . . . . . . . . . 30 2.16 The hardware architecture of FLP-to-LNS conversion . . . . . . . . . . 32 2.17 The conversion errors between the FLP-to-LNS and LNS-to-FLP . . . . 33 2.18 Exponential function diagram . . . . . . . . . . . . . . . . . . . . . . . 34 3.1 SOPC builder flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2 NIOS Embedded Processor . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3 Custom instruction library . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.4 Importation of hardware design from custom instructions . . . . . . . . 39 3.5 CMAC basic architecure . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.6 CMAC separate each input from each memory region . . . . . . . . . . 42 3.7 CMAC architecture using T-S fuzzy model . . . . . . . . . . . . . . . 44 3.8 TS-CMAC algorithm with hybrid number system overall system architecture hardware design . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.9 Hardware design of overall system architecture on SOPC . . . . . . . . 48 4.1 Each of custom instructions LEs consumption diagram . . . . . . . . . 53 4.2 Each of custom instructions delay time diagram . . . . . . . . . . . . . 55 4.3 Each of custom instructions clock cycle diagram . . . . . . . . . . . . . 56 List of Tables 2.1 Expression of IEEE-754 and exception . . . . . . . . . . . . . . . . . . 10 3.1 Importation of hardware design from custom instructions . . . . . . . . 39 4.1 Arithmetic operation verification of software and hardware . . . . . . . 51 4.2 Custom instruction LEs consumption . . . . . . . . . . . . . . . . . . . 52 4.3 Custom instruction delay time . . . . . . . . . . . . . . . . . . . . . . . 54 4.4 Custom instruction clock cycle . . . . . . . . . . . . . . . . . . . . . . . 56[[note]]學號: 602470022, 學年度: 10