The Design and Implementation of a 3.3V 400MHz All Digital Phase-Locked Loop

[[abstract]]This paper is to design and implement an all digital phase-locked loop (ADPLL) circuit. The core of the ADPLL is the switch-tuning digital control oscillator (DCO). Our design of the DCO has features of small hardware cost. This ADPLL has characteristics of fast frequency locking, full digitization, easy design and implementation, and good stability. It is suitable to be used as the clock generator for high performance microprocessors. A prototype of this ADPLL chip is designed and implemented by TSMC's 0.6um SPDM CMOS process. The simulation shows that this chip can operate in the range between 60MHz and 400MHz, and operates at 4x the reference clock frequency. The phase lock process is 47 clock cycles, and the phase error is less than 0.1ns. The chip consists of 4026 MOS transistors and the core size of the VLSI layout is 923.mu.m*921.mu.m.[[sponsorship]]中央研究院; 台灣大學電機工程系; 教育部[[conferencetype]]國內[[conferencedate]]19970821~19970823[[booktype]]紙本[[iscallforpapers]]Y[[conferencelocation]]南投縣, 臺