An Efficient VLSI Architecture for 2-D DWT using Lifting Scheme

[[abstract]]In this paper, we propose a highly efficient VLSI architecture for 2-D lifting-based 5/3 filter discrete wavelet transform (DWT). The architecture is based on the pipelined and folding scheme processing to achieve near 100% hardware utilization ratio and reduce the silicon area. The advantages of the proposed DWT have the characteristics of higher hardware utilization, less memory requirement, and regular data flow. It is suitable for VLSI implementation and can be applied to real-time operating of JPEG2000 and MPEG4 applications.[[sponsorship]]義守大學電機工程學系[[conferencetype]]國際[[conferencedate]]20050428~20050429[[conferencelocation]]高雄, 臺