The new improved pseudo fractional-N clock generator with 50% duty cycle

[[abstract]]Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) to generate the needed frequencies with 50% duty cycle. Further, we propose a design flowchart to solve the problem of pseudo fractional-N clock generator. The circuits are processed in a standard 0.13mum CMOS technology, and work with a supply voltage of 1.2V[[conferencetype]]國際[[conferencedate]]20060521~20060524[[booktype]]紙本[[iscallforpapers]]Y[[conferencelocation]]Island of Kos, Greec