Low Power Multi-Chains Encoding Scheme for SoC in Low-Cost Environment

[[abstract]]In this paper, new compression architecture is proposed for multiple scan-chains. We use buffers to hold back data, and use read enable signals to filter useless data. We use only four extra channels and less hardware for largest ISCAS'89 circuits to reduce test data volume and shift-in power. The average of peak/WTC shift-in turns to 3x/6.6x, after comparing (Wang and Chakrabarty, 2008) and our method. The average of improvement/ hardware is 16%/6%.[[sponsorship]]IEEE Computer Society Test Technology Thchnical Council; IEEE Philadelphia Section[[conferencetype]]國際[[conferencedate]]20091101~20091106[[booktype]]紙本[[booktype]]電子版[[iscallforpapers]]Y[[conferencelocation]]Austin, Texas US