專利國別:美國United States Patent: 7,242,231Application number: 11/232,949國際分類號:H03L 7/06[[abstract]]Clock generators capable of generating clocks with different frequency according to a binary code. A voltage controlled oscillation module generates a plurality of first clocks (D.sub.0.about.D.sub.m) with a first frequency (f0), in which the first clocks D.sub.i and D.sub.i-1 have a fixed phase difference and 1<i<m. A logic control circuit outputs a set of corresponding clocks arranged in a corresponding sequence according to the first clocks and a binary code. A clock synthesizer generates a second clock with a second frequency (f1) according to the set of corresponding clocks, in which f1=A/B f0, A<B and A and B are positive integers
A delay-locked loop (DLL) based fractional-N frequency synthesizer with a programmable injection clo...
[[abstract]]This work presents a clock generator with cascaded dynamic frequency counting (DFC) loop...
The phase selection technique is a good solution to design programable dividers widely used in fract...
[[abstract]]Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in s...
[[abstract]]A proposed synthesizable pseudo fractional-N clock generator with improved duty cycle ou...
[[abstract]]A proposed pseudo fractional-N clock generator with 50% duty cycle output is presented b...
[[abstract]]Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in s...
[[abstract]]Because system-on-a-chip (SOC) needs multiple clocks and mostly with 50% duty cycle in t...
We have designed and implemented an SFQ programmable clock generator (PCG), which can generate the v...
textAn architecture and design of a Phase Locked Loop based frequency synthesizer is developed in t...
Abstract−In this paper, a novel architecture of a fractional-N phase-locked loop (PLL) is presented ...
Although multiplying delay-locked loops allow clock frequency multiplication with very low phase noi...
Abstract—This work presents a clock generator with cascaded dynamic frequency counting (DFC) loops f...
This report describes the design of a Clock Generator Chip. The purpose of this chip is to generate ...
ABSTRACT This paper presents a circuit of a high-precision, wide ranged, analog clock generator wit...
A delay-locked loop (DLL) based fractional-N frequency synthesizer with a programmable injection clo...
[[abstract]]This work presents a clock generator with cascaded dynamic frequency counting (DFC) loop...
The phase selection technique is a good solution to design programable dividers widely used in fract...
[[abstract]]Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in s...
[[abstract]]A proposed synthesizable pseudo fractional-N clock generator with improved duty cycle ou...
[[abstract]]A proposed pseudo fractional-N clock generator with 50% duty cycle output is presented b...
[[abstract]]Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in s...
[[abstract]]Because system-on-a-chip (SOC) needs multiple clocks and mostly with 50% duty cycle in t...
We have designed and implemented an SFQ programmable clock generator (PCG), which can generate the v...
textAn architecture and design of a Phase Locked Loop based frequency synthesizer is developed in t...
Abstract−In this paper, a novel architecture of a fractional-N phase-locked loop (PLL) is presented ...
Although multiplying delay-locked loops allow clock frequency multiplication with very low phase noi...
Abstract—This work presents a clock generator with cascaded dynamic frequency counting (DFC) loops f...
This report describes the design of a Clock Generator Chip. The purpose of this chip is to generate ...
ABSTRACT This paper presents a circuit of a high-precision, wide ranged, analog clock generator wit...
A delay-locked loop (DLL) based fractional-N frequency synthesizer with a programmable injection clo...
[[abstract]]This work presents a clock generator with cascaded dynamic frequency counting (DFC) loop...
The phase selection technique is a good solution to design programable dividers widely used in fract...