[[abstract]]A carry-free subtractive division algorithm is proposed in this paper. In the conventional subtractive divider, adders are used to find both quotient bit and partial remainder. Carries are usually generated in the addition operation, and it may take time to finish the operation, therefore, the carry propagation delay usually is a bottleneck of the conventional subtractive divider. In this paper, a carry-free scheme is proposed by using signed bit representation to represent both quotient and partial remainder. During the arithmetic operation, a special technique is used to decide the quotient bit, and the new partial remainder can be found further by a table lookup-like method. The signed bit format of the quotient can be conver...
Almost all recent microprocessors and DSP chips perform addition, subtraction, multiplication and di...
ISBN: 0818689633International audienceThe authors deal with the detailed VLSI implementation of a fa...
A division algorithm in which the quotient-digit selection is performed by rounding the shifted resi...
This paper presents a derivation of four radix-2 division algorithms by digit recurrence. Each divis...
[[abstract]]In recent years, computer applications have increased in the computational complexity. T...
The speed of SRT-type dividers is mainly determined by the complexity of the quotient-digit selectio...
ISBN: 0818669055The digit-recurrence division relies on a sequence of addition/subtraction and shift...
[[abstract]]A novel floating-point division architecture with IEEE 754-1985 standard is proposed in ...
[[abstract]]A new floating-point division architecture that complies with the IEEE 754-1985 standard...
ISBN: 0818669055The development of a new general radix-b division algorithm, based on the Svoboda-Tu...
In this paper, we propose a class of division algorithms with the aim of reducing the delay of the s...
Includes bibliographical references (page 143)This project details the theory and hardware implement...
: The digit-recurrence division relies on a sequence of addition/subtraction and shift operations i...
We present a radix-8 divider that uses an over-redundant digit set for the quotient in order to obta...
This paper presents the design of a radix-4, 32-bit integer divider which uses a recursive, non-rest...
Almost all recent microprocessors and DSP chips perform addition, subtraction, multiplication and di...
ISBN: 0818689633International audienceThe authors deal with the detailed VLSI implementation of a fa...
A division algorithm in which the quotient-digit selection is performed by rounding the shifted resi...
This paper presents a derivation of four radix-2 division algorithms by digit recurrence. Each divis...
[[abstract]]In recent years, computer applications have increased in the computational complexity. T...
The speed of SRT-type dividers is mainly determined by the complexity of the quotient-digit selectio...
ISBN: 0818669055The digit-recurrence division relies on a sequence of addition/subtraction and shift...
[[abstract]]A novel floating-point division architecture with IEEE 754-1985 standard is proposed in ...
[[abstract]]A new floating-point division architecture that complies with the IEEE 754-1985 standard...
ISBN: 0818669055The development of a new general radix-b division algorithm, based on the Svoboda-Tu...
In this paper, we propose a class of division algorithms with the aim of reducing the delay of the s...
Includes bibliographical references (page 143)This project details the theory and hardware implement...
: The digit-recurrence division relies on a sequence of addition/subtraction and shift operations i...
We present a radix-8 divider that uses an over-redundant digit set for the quotient in order to obta...
This paper presents the design of a radix-4, 32-bit integer divider which uses a recursive, non-rest...
Almost all recent microprocessors and DSP chips perform addition, subtraction, multiplication and di...
ISBN: 0818689633International audienceThe authors deal with the detailed VLSI implementation of a fa...
A division algorithm in which the quotient-digit selection is performed by rounding the shifted resi...