[[alternative]]適用於行動通訊及無線網路之寬頻低功率三角積分調變器之設計與實現

碩士[[abstract]]在現代行動通訊及無線網路系統的應用上，類比/數位轉換器(A/D Converter)在其系統中扮演極其重要的角色。超取樣和雜訊移頻技術則是早已被應用於現代超大型積體電路中的類比數位轉換介面，由於超取樣的特性，使得三角積分調變器通常都被限制在音頻信號的應用上。而隨著超大型積體電路製程的改良，使許多的研究逐漸轉移到寬頻帶的應用上，如802.11a、xDSL、Bluetooth、GSM及WCDMA等。 在現代行動通訊及網路系統對高頻寬的需求下，一般傳統的低階三角積分調變器已經無法勝任這高頻寬的需求，所以高階且多位元的三角積分調變器在高頻寬系統上是必須的。而產品未來的發展導向將朝向體積小巧、價格低廉、及較長的待機時間發展，因此SOC(System-on-Chip)及低功率消耗的設計概念將是未來無線寬頻及行動通訊技術發展的不可或缺的兩個要素。 本論文所研究的方向為設計並實現適用於GSM及WCDMA的雙頻帶三角積分器及適用於802.11a系統下之寬頻低功率三角積分調變器。在設計考量上由於類比電路中的積分器會產生許多非理想的誤差，如有限的直流增益,電容偏差...等等，這些電路上的非理想誤差會對我們的高階三角積分調變器造成很大的影響，在本論文中我們將這些非理想的誤差用Matlab及Simulink這兩套軟體來將其加入我們的模型中,以期達到更精準的高階三角積分調變器性能。而且由於我們可以由此模型訂出我們最佳化的係數及電路規格，這樣便可以大大的節省設計的時間。而且在電路實現時也會有設計的準則及目標。 本篇論文所提出之應用於GSM及WCDMA的雙頻帶三角積分調變器，已在0.18微米1P6M標準製程中實現，工作電壓為1.8V，GSM及WCDMA的寬頻分別為200KHz及2MHz，取樣頻率為32MHz，超取樣比為80及8，量測結果顯示其動態輸入範圍為76及68dB，在WCDMA模式下功率消耗為28mW。另一個應用於802.11a系統下之寬頻低功率三角積分調變器，將在0.18微米1P6M標準製程加以設計實現，工作電壓為1.8V，寬頻為10MHz，取樣頻率為160MHz，超取樣比為8，模擬結果顯示在取樣頻率160MHz下其動態輸入範圍為74dB，而最大的訊號雜訊失真比為70dB，總功率消耗38mW。[[abstract]]In the applications for the modern communication and wireless network systems, the analog-to-digital (A/D) converters play an important role in the systems. The over-sampling and noise shaping techniques are used in analog to digital conversion interface of modern very-large-scaled integrated circuits. Due to over-sampling characteristics, the delta sigma (ΔΣ) modulators usually are limited on the application of voice band signals. As the integrated circuits process improvement, it makes many researches transfer to applications of wide-bandwidth gradually, such as 802.11a, xDSL, Bluetooth, GSM, and WCDMA. Analog-to-digital converters based on the delta ΔΣ modulators have become popular in various applications. Due to the wide bandwidth requirement of modern communication and network, however, the low-order single-bit ΔΣ modulator cannot suit in wide bandwidth applications. Therefore, the high-order multi-bit ΔΣ modulator is necessary in wide bandwidth applications. With the improvement of the VLSI technique, all of these modules are expected to integrate for less chip area, low cost, and low power consumption. Therefore, the SOC (System on a Chip) and low power consumption are the most important concepts in the development for the modern communication and network systems. In this thesis, we want to design wideband, lower power delta sigma modulator for WCDMA and GSM dual bandwidth and 802.11a applications. Furthermore, the circuit non-idealities effects also can be included in our architectures to predict the final performance of actual the ΔΣ modulators. According to these non-idealities models and analyses, we can obtain the optimum circuit specifications to implement our ΔΣ modulators. Therefore, the design cycle time can be reduced effectively and the circuits also can be implemented based on these optimum specifications. In this thesis, a wideband, lower power ΔΣ modulator for W-CDMA and GSM dual bandwidth application is implemented in a standard 0.18-μm 1P6M CMOS technology. For the W-CDMA applications, the measurements indicate a dynamic range of 68dB and a SNDR of 61dB. For the GSM applications, the measurements indicate a dynamic range of 76dB and a SNDR of 70dB. The core area is 0.84mm2, and the power consumption is 28-mW at 1.8V. Another lower power ΔΣ modulator in applications of 802.11a is implemented in a standard 0.18-μm 1P6M CMOS technology, too. The simulation results show that the bandwidth is 10MHz；the sampling frequency is 160MHz；the dynamic range and the peak signal to noise ratio are 74dB and 70 dB respectively, and the total power dissipation is 38-mW at 1.8V.[[tableofcontents]]Chapter 1：Introduction 1 1.1 Motivation and Applications 1 1.1.1 Dual-Standard of GSM and WCDMA System 3 1.1.2 Wireless LAN 802.11a System 5 1.2 Thesis Structure 6 Chapter 2：Architecture Study of Delta Sigma Converters 8 2.1 Introduction 8 2.2 Motivations for Delta Sigma Modulator Converters 9 2.2.1 Quantization 9 2.2.2 Oversampling Technique 14 2.2.3 Noise Shaping Delta Sigma Modulator 17 2.3 Wideband Delta Sigma Modulator Architecture 19 2.3.1 Single-Loop Architecture 20 2.3.2 Interpolative Architecture 21 2.3.3 Multi-stage Cascaded Delta Sigma Modulator 25 2.3.4 Multi-Bit Noise Shaping Delta Sigma Modulator 26 2.4 Summary 29 Chapter 3：Dual-Mode WCDMA/GSM Delta Sigma Modulator 30 3.1 Introduction 30 3.2 System Level Design 30 3.2.1 Dual-Band Modulator 32 3.2.2 Low-Distortion and Swing-Suppression Topology 33 3.2.3 Multi-bit DAC Mismatches 34 3.3 Circuit Level Design 35 3.3.1 Design of the OTA 39 3.3.2 Design of the four bit Quantizer 43 3.3.3 Design of the Clock Generator 45 3.4 Simulation Results 46 3.5 Experimental Results 47 3.5.1 Test Setup 47 3.5.2 Layout and Pin assignment 49 3.5.3 Measurement Results 51 Chapter 4：A 20-MSample/s Sigma Delta modulator for 802.11a 54 4.1 Introduction 54 4.2 System Level Design 55 4.3 Circuit Level Design 58 4.3.1 OTA Design 62 4.3.2 Design of the Clock Generator 64 4.4 Simulation Results 65 4.5 Experimental Consideration 67 4.5.1 Test Setup 67 4.5.2 Layout and Pin Assignment 67 4.6 Conclusion 70 Chapter 5：Conclusion and Future Work 71 5.1 Conclusion 71 Reference 72 Chapter 1 Figure 1.1 Wideband Receiver for Dual-Standard System 4 Chapter 2 Figure 2.1 (a) model of the quantizer (b) The linear model, (c) input-output characteristic of a B-bit quantizer, (d) and one-bit quantizer (e) The quantization error of a B-bit quantizer, (f) and one-bit quantizer 10 Figure 2.2 (a) Probability Density Function (PDF) and (b) Power Spectral Density (PSD) of the quantization error, (c) Transfer function of the quantization error to the output 13 Figure 2.3 Illustrating the benefits of oversampling (a) Sampled quantizer symbol and approximated PSD of the quantization error; (b) In-band error power and total error power 16 Figure 2.4 (a) General structure of a noise-shaping ADC and (b) its linearized mode 17 Figure 2.5 The PSD of the quantization noise PDSEq(ω) for different converter 19 Figure 2.6 The Single-Loop L-Order Delta Sigma Modulator 20 Figure 2.7 Pole and Zero locations and NTF frequency response 21 Figure 2.8 Distributed feedback with a forward input and resonator feedback 22 Figure 2.9 Feedforward summation with a forward input and resonator feedback 22 Figure 2.10 Pole and Zero locations and NTF frequency response of the Butterworth alignment 23 Figure 2.11 Pole and Zero locations and NTF frequency response of the Inverse Chebyshev alignment 24 Figure 2.12 Pole and Zero locations and NTF frequency response of the Elliptic alignment 24 Figure 2.13 General structure of a cascaded delta-sigma modulator 26 Figure 2.14 A linear model of multi-bit modulator with DAC errors 28 Chapter 3 Figure 3.1 The frequency responses 31 Figure 3.2 The proposed multi-noise shaping (MNS) ΔΣ modulator architecture 33 Figure 3.3 The output spectrum with 1% DAC mismatch 35 Figure 3.4 Block diagram of the implemented Fifth-order multi-noise-shaping modulator 36 Figure 3.5 The schematic of the first stage 2nd-order Delta Sigma Modulator 37 Figure 3.6 SC realization of the summation at the quantizer input in Fig 35 37 Figure 3.7 (a) the 1st integrator (b) the 2nd and 3rd integrator (c) the summing integrator of the interpolative delta sigma modulator in the cascaded-stage 39 Figure 3.8 The folded-cascode OTA (a) with gain-boosted (b) without gain-boosted 41 Figure 3.9 The Bias circuit of OTA 42 Figure 3.10 The schematic of the CMFB circuit 42 Figure 3.11 The schematic of four bit quantizer 44 Figure 3.12 The schematic of switched-capacitor comparator 45 Figure 3.13 The schematic of comparator circuit 45 Figure 3.14 The schematic of clock generator circuit 46 Figure 3.15 The spectrum of the MNS modulator simulation (a) in HSPICE and(b) comparison with MATLB for GSM application Simulation (c) in HSPICE and (d) comparison with MATLB for W-CDMA application 47 Figure 3.16 Experimental test setup 48 Figure 3.17 (a) Regulator circuit (b) Reference voltage circuit (c) The filter tank for the supply voltages 48 Figure 3.18 The die photo of the MNS modulator 49 Figure 3.19 (a) Pin configuration diagram and (b) Pin assignments of the chip 50 Figure 3.20 The photograph of the PC board for measurement 51 Figure 3.21 The digital output bit streams 52 Figure 3.22 Measured output power spectra of the modulator (a) for GSM and (b) WCDMA application 52 Figure 3.23 Measured SNDR vs Input power 53 Chapter 4 Figure 4.1 The schematic of the fifth order single loop Delta Sigma Modulator 56 Figure 4.2 SNSR vs jitter 57 Figure 4.3 SNDR vs KT/C 57 Figure 4.4 (a) SNDR vs nonlinearly finite gain (b) Mathematical model of the nonlinear gain 58 Figure 4.5 (a) First integrator stage, (b) Second integrator stage, (c) Third integrator stage, (d) Fourth integrator stage (e) Fifth integrator stage 60 Figure 4.6 3-bit quantizer combine with sc summation 61 Figure 4.7 control circuit 62 Figure 4.8 The schematic of the telescopic amplifiers 63 Figure 4.9 The schematic of clock generator circuit 65 Figure 4.10 Output spectrum of the modulator (post layout simulation) 66 Figure 4.11 The dynamic range of the modulator 66 Figure 4.12 Experimental test setup 68 Figure 4.13 Layout of the experimental modulator 68 Figure 4.14 (a) Pin configuration diagram and (b) Pin assignments of the chip 69 Table 1.1 The receiver specifications for GSM and WCDMA System 5 Table 1.2 The specifications for Wireless LAN 6 Table 3.1 The second stage coefficients of capacitors 39 Table 3.2 The gain-boosted folded-cascode OTA MOS size 41 Table 3.3 The folded-cascode OTA MOS size 41 Table 3.4 Performance summary of the OTAs 43 Table 3.5 Performance summary of the DSM 53 Table 4.1 Influences of the non-idealities 57 Table 4.2 The coefficients of capacitors 60 Table 4.3 The corresponding table of thermometer code and active code 61 Table 4.4 Performance summary of the telescopic OTA 64 Table 4.5 Performance Summary 66 Table 4.6 ΔΣ modulator performance comparisons 67[[note]]學號: 692390932, 學年度: 9