[[alternative]]動態指定測試資源設計之系統晶片測試

碩士[[abstract]]由於半導體產業的蓬勃發展，台灣已從早期的晶圓代工時代逐漸轉換為IC設計工業。隨著產業的轉型，如今，台灣的IC設計也跟隨著世界IC產業的腳步，發展整合型的功能晶片，即系統晶片(System on Chip)。一顆系統晶片有相當高的複雜度，主要基本的架構包含了：中央處理單元(CPU, Center Possess Unit)；記憶單元(RAM , ROM)；運算邏輯單元(ALU, Arithmetic Logic Unit)；資料匯流排和輸入輸出的部份。此外，設計系統晶片時，會依照晶片功能的需求，加入許多不同的矽智財(IP, Intellectual Properties)，來完成一個整合型的積體電路。不過，當晶片是經由各種矽智財所組合而成時，晶片的測試就變的格外的重要和困難。一顆晶片假設沒有經過測試是沒辦法令人信服而使用；系統晶片亦是如此。系統晶片測試的困難點主要是在於系統晶片中的矽智財各自需要測試，整合成的完整晶片也要測試。如此就需要增加額外的硬體設計，和撰寫所應搭配的演算法程式。 學生此篇論文主要是在設計測試排程的部份，也就是排程演算法的撰寫。我們主要是將系統晶片中的每各矽智財(稱之Core)，再更進一步的拆成一片一片的進行測試。在排程中，隨著現在時間(current time)的改變，時間點上的測試資源(TAM)的數量也有所不同；因此，Core的測試也就隨著測試資源(TAM)數量而改變。如此，一個Core的測試排程會宛如階梯的形狀，我們稱之為梯狀排程(Stairway Schedule)。 在我們的演算法中，我們利用傳統階梯點的計算去產生我們初始Core矩形的型態。再使用二維箱子放置問題的演算法跟我們提出的梯狀排程的方法去完成整個測試。而加入我們的想法之後，可以減少測試排程中空窗時間(Idle Time)的發生，使的整體測試應用時間得以縮減。[[abstract]]Test access mechanism (TAM) and test schedule for System-On-chip (SOC) are challenging problems. Test schedule must be effective to minimize testing time, under the constraint of test resources. This paper presents a core section method based on generalized 2-D rectangle packing. A core cuts into many pieces and utilizes the design of reconfigurable core wrappers, and is dynamic to change the width of the TAM executing the core test. Therefore, a core can utilize different TAM width to complete test.[[tableofcontents]]Table of Contents 誌謝……………………………………………………………………………….…..II 中文摘要…………………………………………………………………………….III 英文摘要……………………………………………………………………………...V Table of Contents…………………………………………………………………...VI List of Figures…………………………………………………………………….VIII List of Tables……………………………………………………………………..….X Chapter1: Introduction………………………………………………………………1 1.1 Core-based Design………………………………………………………………...1 1.1.1 The evolution of design flow………………………………………………..2 1.2 Test challengers in Core-based SOC designs……………………………………..4 1.2.1 Board test versus core test…………………………………………………..5 1.2.2 Core test access……………………………………………………………...9 Chapter2: TAM architecture and Wrapper Design……………………………...11 2.1 Test access architecture…………………………………………………………..11 2.2 TAM architecture introduction……………………………………………...........12 2.2.1 Basic TAM architecture……………………………………………………12 2.2.2 Test bus architecture……………………………………………………….14 2.2.3 TestRail architecture……………………………………………………..…15 2.3 DFT (Design foe Testability)………………………………………………..…...17 2.3.1 Scan chain……………………………………………………………….…17 2.3.2 Core test time………………………………………………………………17 2.4 Test wrapper design……………………………………………………………...20 2.4.1 Wrapper architecture……………………………………………………….20 2.4.2 Wrapper design problem………………………………………………...…21 2.4.3 Design wrapper algorithm……………………………………………….…23 2.4.4 Patero-optimal points………………………………………………………27 Chapter3: Reconfigurable Core Wrappers Design.………………………………29 3.1 The Reconfigurable core wrappers introduction……….………………………...29 3.2 An improvement of reconfigurable core wrappers ………………………………32 Chapter4: Rectangle Packing problem and Test scheduling…………………….35 4.1 2-D bin packing model...…………………………………………………………35 4.2 The Popular Rectangle Packing Model…………..………………………………36 4.3 The General Test Scheduling…………………………………………………….38 4.3.1 The Serial Test Schedules………………………………….........................39 4.3.2 The Parallel Test Schedules………………………………………………..39 4.3.3 The Mixed test schedules…………………………………..........................40 4.4 Using dynamic TAM width to test a core and the stairway test scheduling……..41 Chapter5: Algorithm for solve the problem of Test scheduling…………………43 5.1 The design follow of our algorithm…………………………………..………….43 5.2 Our algorithm explain……………………………………………...…………….46 5.2.1 The Structure of the core….…………………………………………….…46 5.2.2 The Initial rectangle of the core……………………………………………46 5.2.3 A first movement of scheduling the core…………………………………47 5.2.4 Assigning the idle TAM width to cores…………………………………..47 5.2.5 Using the action of stairway schedule the core……….………………..…47 5.2.6 The idle time of the stairway scheduling…………………………………48 Chapter6: Experimental Results…………………………………………………..49 Chapter7: Conclusions…………………………………………………………..…51 References………………………………………………………………………..…52 List of Figures Chapter 1 Figure 1.1 An example of SOC ……………………………………………………1 Figure 1.2 A simplified chip design flow and industry relationships………………3 Figure 1.3 System design flow using core cells……………………………………4 Figure 1.4 (a) system-on-Board, (b) system-on-Chip trajectory…………………...6 Figure 1.5 An example of boundary scan for SOB…………………………………7 Figure 1.6 Overview of the test access in an embedded-core test…………………10 Chapter 2 Figure 2.1 The test access architecture overview…………………………………12 Figure 2.2 (a) Multiplexing Architecture. (b) Daisychain Architecture, (c) distribution Architecture…..………………………………………14 Figure 2.3 (a) A Test Bus Architecture (b) A possible corresponding serial test schedule……………………..15 Figure 2.4 (a) A TestRail Architecture, (b) A possible corresponding serial, (c) A parallel test schedules…………………………………………...16 Figure 2.5 An overview of scan chain………….……………………………..…..17 Figure 2.6 An example of core test time………………………………………….19 Figure 2.7 Core test wrapper…………………………...........................................21 Figure 2.8 Wrapper chains: (a) unbalanced, (b) balanced………...……...……….22 Figure 2.9 (a) Wrapper design example using four wrapper scan chains, (b) Two wrapper scan chains………………………………………… 23 Figure 2.10 The pseudo code for Algorithm Design_wrapper……………………..25 Figure 2.11 The pareto-optimal points for core 6 in SOC p93791……………...….28 Chapter 3 Figure 3.1 The graph of the reconfigurable core………………………………….30 Figure 3.2 The graph of the reconfigurable core (G1 G2 G3)…………..30 Figure 3.3 The configuration of reconfigurable core wrapper.................................31 Figure 3.4 The reconfigurable core wrapper (TAM width 1 bit)………………….31 Figure 3.5 The reconfigurable core wrapper (TAM width 2 bits)...........................31 Figure 3.6 Additional multiplexer before the head and after the tail of all scan chains…………………………………….............................................32 Figure 3.7 Control signal are selected as a one (TAM width = 1)………………...33 Figure 3.8 TAM width = 2………………………………………………………...33 Figure 3.9 Control signal are selected as a zero (TAM width = 3)………………..33 Chapter 4 Figure 4.1 A rectangle transformation for a core………………………………….35 Figure 4.2 SOC 2-D pin packing model………………………………………......35 Figure 4.3 A TAM design using TAM width partition…………………………....36 Figure 4.4 Test schedule of Figure 4.3……………………………………………36 Figure 4.5 An example rectangle for Core 6 in SOC p9379……………………...37 Figure 4.6 TAM design using generalized rectangle packing……………………..38 Figure 4.7 Test schedule of Figure 4.6…………………………………………….38 Figure 4.8 An example of the serial test schedules………………………………..39 Figure 4.9 An example of the parallel test schedules……………………………..40 Figure 4.10 An example of the mixed test schedules…………………………..…..40 Figure 4.11 The SOC test scheduling (the past method)……..…………………….41 Figure 4.12 The SOC test of stairway scheduling………………………………….42 Chapter 5 Figure 5.1 The design follows of basic test scheduling (no stairway scheduling)...43 Figure 5.2 The design follows of test scheduling (stairway scheduling)………….44 Figure 5.3 Algorithm for solve the problem of test scheduling…………………...45 Figure 5.4 The data structure of the core………………………………………….46 Figure 5.5 Assign the remnant TAM width to the longest core…………………..47 Figure 5.6 The idle time of the stairway scheduling……………………………...48 List of Tables Table 2.1 The results of procedure Design_wrapper for core 6 in SOC p93791……………………………………………………………..…...26 Table 1 Experimental results for SOC d695……………………………………49 Table 2 Experimental results for SOC p22810…………………………………49 Table 3 Experimental results for SOC p34392……………...……………….…50 Table 4 Experimental results for SOC p93791…………………………………50[[note]]學號: 693390220, 學年度: 9