Enhanced write performance of a 64-Mb phase-change random access memory
- Oh, Hyung-rok
- Cho, Beak-hyung
- Cho, Woo Yeong
- Kang, Sangbeom
- Choi, Byung-gil
- Kim, Hye-jin
- Kim, Ki-sung
- Kim, Du-eung
- Kwak, Choong-keun
- Byun, Hyun-geun
- Jeong, Gi-tae
- Jeong, Hong-sik
- Kim, Kinam
Publication date
January 2006
DOI Publisher
Institute of Electrical and Electronics Engineers (IEEE) ISSN
0018-9200 Journal
IEEE Journal of Solid-State CircuitsAbstract
The write performance of the 1.8-V 64-Mb phase-change random access memory (PRAM) has been improved, which was developed based on 0.12-mu m CMOS technology. For the improvement of RESET and SET distributions, a cell current regulator scheme and multiple step-down pulse generator were employed, respectively. The read access time and SET write time are 68 ns and 180 ns, respectively
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