支援ARM資料處理指令之SIMD技術為基礎的軟體實現錯誤容忍之研究;SIMD-Based Software Fault Tolerance for ARM Data-Processing Instructions

[[abstract]]指令層級的軟體容錯技術是一種比使用硬體實作更具有低花費且高彈性的技術，此技術是當瞬時錯誤發生時，透過重複執行指令來複製至少三份的副本以進行錯誤的偵測與修復，然而重複執行相同指令卻也是造成執行效能下降的主要原因之一。現今大部分的嵌入式系統和手持移動裝置都運行在ARM處理器架構上，然而目前很少研究是針對ARM處理器的容錯技術。在這篇論文中，我們針對ARM處理器的資料處理指令，開發以SIMD為基礎的軟體容錯技術，其核心技術在於透過SIMD指令優化重複執行指令的效能，以提升程式的可靠度。最後，我們透過LLVM編譯器來實作，並能夠自動地產生具有容錯能力的程式。實驗結果顯示，我們所提出的方法可以正確的產生容錯程式，而執行效能比原始版本下降4%-70%，程式碼大小比原始版本大上1.1-2.5倍。 Software-based instruction-level redundant execution is a cost-efficient and flexible technique to tolerate transient faults compared to use hardware implementation. It duplicates at least three copies of data to recover errors when system failure. However, redundancy execution is the main reason for performance degradation. The ARM architecture is widely used in nowadays embedded systems and mobile devices. However, few studies focus on instruction-level redundant execution of ARM processor. In this thesis, we develop a SIMD-based software fault tolerance technique for ARM data-processing instructions. The core technique employs instruction-level redundant execution with SIMD optimization to tolerate single bit-flipping errors. The proposed approach is implemented in the LLVM compiler to generate protected code automatically. For the tested benchmark programs, preliminary experiments show that the proposed approach can correctly generate fault-tolerant codes at costs of 4%–70% performance degradation on average compared with the original versions. The fault-tolerant versions of code are 1.1–2.5 times larger than the original versions