抗變異自適性調壓迴路控制設計;Variation-Resilient Adaptive Voltage Scaling Control Loop Design

[[abstract]]欲推估參數下自適性電壓調控系統的結果傳統上須透過長時模擬才能得到一組參數的之預期結果，預先錯誤自適性電壓調控系統提出使用馬可夫模型讓參數對於自適性電壓調控系統的影響可透過簡易數學式完成推估，只需要一次性不同電壓下的延遲分布模擬，因此能夠快速的分析不同組參數對於自適性電壓調控系統的影響。本篇論文實作一個90nm晶片驗證預先錯誤自適性電壓調控系統，並使用馬可夫模型搭配10萬筆運算數量以及每20mV為一單位的不同電壓下之延遲分布，其推估之結果與實際之自適性電壓調控結果之電壓分布誤差為34.86%，但延遲分布使用1千萬筆pattern數量時其推估的結果與實際之電壓分布誤差為2.78%，此原因為模擬的延遲分布尾端資訊不足使得推估電壓機率有誤差。提出使用1千筆運算數量之延遲分布配合近似之高斯分布模型取代模擬10萬筆運算數量之延遲分布解決上述延遲分布尾端資訊不足之原因，其推估的結果與實際自適性電壓調控系統結果之電壓分布誤差為5.68%，分析參數 (N,、nlimit↓、nlimit↑)，其分析結果為N> nlimit↓> nlimit↑，透過控制參數調整錯誤率時，建議將nlimit↓設成1後且nlimit↑設成N*2%，透過調整N達到預期的效果，並以晶片驗證平均錯誤率落在10-2 到10-5 範圍。 Traditionally, to estimate one of AVS control parameters of AVS results takes large simulation time, pre-error AVS system have been proposed to simplify the procedure of estimate AVS result, which just simulated delay distributions at different voltage for once with Markov chain to estimate all set of AVS control parameters of AVS result. In this paper, we evaluate pre-error AVS system in 90nm CMOS, using delay distributions of 100,000 patterns and 20mV step voltage and Markov chain to estimate the AVS result which the error of RMSE of voltage scatter with AVS in 90nm CMOS is 34.86%, but the error of RMSE of voltage scatter with AVS in 90nm CMOS is 2.78% while increasing the patterns to 10,000,000 patterns, the reason of this difference is the tail information of delay distribution is not enough (i.e. limit precision). We proposed using delay distributions of 1,000 patterns with Interpolate Gaussian mathematic model to replace delay distributions of 100,000 patterns to estimate AVS results which the error of RMSE of voltage scatter with AVS in 90nm CMOS is 5.68%. We also analysis the sensitivity of AVS control parameters (N, nlimit↓, nlimit↑) which the result is N> nlimit↓> nlimit↑, therefore, fixed n_lb=1, n_ub=N*2% and adjust N to get the difference error rate from control parameters, and evaluate the adjust method in 90nm CMOS to get the error rate from 10-2 to 10-5