功率放大器輸出端主動變壓器結構設計與氮化鎵功率放大器線性度分析;Active Transformer Matching Design of Power Amplifier and Linearity Analysis of GaN Power Amplifier

[[abstract]]本論文包括兩部分電路設計，第一部分是以CMOS 90 nm製程設計一應用在50 GHz (V Band)之功率放大器，輸出端利用具結合功率效果之變壓器結構阻抗轉換器設計。第二部分以氮化鎵高電子移動率電晶體設計一具效率與線性度之功率放大器，此功率放大器使用由AB類與C類放大器所組成之Doherty架構。第一部分設計的CMOS毫米波功率放大器其輸出匹配利用變壓器之特性設計功率結合器與阻抗轉換器，其原因為在高阻抗轉換比的情況下，傳統LC匹配網路之損耗會隨之增加，而變壓器之損耗與阻抗轉換比為獨立的，而本論文設計之變壓器可將兩組差動對放大器之功率結合並輸出，模擬電路之損耗在50GHz時為1.7 dB。而此電路之量測結果在50 GHz時電路增益為7.8 dB，輸出1 dB增益壓縮點為5.7 dBm，而飽和輸出功率為10.2 dBm。小訊號參數S21在50 GHz到67 GHz之間皆大於8 dB。第二部分設計的電路為Doherty功率放大器，由於傳統功率放大器操作在高效率區時線性度很差，反之操作在高線性區時效率也不會好，而此架構則是利用輸出端之主動式負載修正技術，以及結合AB類與C類放大器之特性，使得功率放大器輸出飽和點回退6 dB時還能保持高效率的特性，且不失線性度。本論文中設計出一具效率與線性度之功率放大器，其結果為當雙頻量測時輸出功率為36 dBm時的三階交互調變失真為-30 dBc以下，單頻輸出功率37 dBm時效率為41.9 %。 This thesis includes two parts, the first part is a 50 GHz (V band) power amplifier designed by CMOS 90 nm process. The output matching circuit is a transformer based impedance converter with a power combining structure. The second part is focused on the design of a GaN HEMT-based power amplifier with high efficiency and high linearity. The architecture is Doherty power amplifier, which is consisting of Class AB and Class C amplifiers.In the first part, the output matching of the CMOS millimeter wave power amplifier using the characteristics of the transformer plays as a power combiner and impedance converter. As in the case of high impedance-conversion ratio, the loss of the traditional LC matching network will be higher, and the loss of transformer is independent on impedance conversion ratio. The transformer not only converts the impedance but also combine the deleivered power of two sets of differential amplifiers, and the simulated loss of the transformer is about 1.7 dB at 50 GHz. This power amplifier as measured at 50 GHz, the circuit gain is 7.8 dB, the output 1 dB gain compression point is 5.7 dBm, and the saturated output power of 10.2 dBm. The s-parameter measurement shows the gain being greater than 8 dB between 50 GHz and 67 GHz.The second part of this thesis is the design of Doherty power amplifier. As the traditional power amplifier operation in the high efficiency region when the linearity is poor, otherwise, operating in the high linearity region, the efficiency of power amplifier will not be good. Doherty architecture uses active load modification at output port, and combines the characteristics of Class AB and Class C amplifier. So that the overall characteristic of power amplifier can maintain high efficiency without losing the linearity under the output power back off 6 dB from the saturation point. The measured result indicates that the third-order intermodulation distortion is lower than -30 dBc when the output power of the two-tone measurement is 36 dBm, and the one-tone output power is 37 dBm when the efficiency is 41.9 %