10 Gbps TCP/IP streams from the FPGA for the CMS DAQ eventbuilder network
- Bauer, Gerry P
- Bawej, T
- Behrens, U
- Branson, J
- Chaze, O
- Cittolin, S
- Coarasa, J A
- Darlea, Georgiana-Lavinia
- Deldicque, C
- Dobson, M
- Dupont, A
- Erhan, S
- Gigi, D
- Glege, F
- Gomez-Ceballos, G
- Gomez-Reino, R
- Hartl, C
- Hegeman, J
- Holzner, A
- Masetti, L
- Meijers, F
- Meschi, E
- Mommsen, R K
- Morovic, S
- Nunez-Barranco-Fernandez, C
- O'Dell, V
- Orsini, L
- Ozga, W
- Paus, Christoph M. E.
- Petrucci, A
- Pieri, M
- Racz, A
- Raginel, Olivier
- Sakulin, H
- Sani, M
- Schwick, C
- Spataru, A C
- Stieger, B
- Sumorok, Konstanty C
- Veverka, Jan
- Wakefield, C C
- Zejdl, P
Publication date
May 2019
DOI Publisher
IOP Publishing Journal
Journal of InstrumentationAbstract
For the upgrade of the DAQ of the CMS experiment in 2013/2014 an interface between the custom detector Front End Drivers (FEDs) and the new DAQ eventbuilder network has to be designed. For a loss-less data collection from more then 600 FEDs a new FPGA based card implementing the TCP/IP protocol suite over 10Gbps Ethernet has been developed. We present the hardware challenges and protocol modifications made to TCP in order to simplify its FPGA implementation together with a set of performance measurements which were carried out with the current prototype
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