A study of the effect of memory system configuration on the power consumption of an FPGA processor

With electrical energy being a finite resource, feasible methods of reducing system power consumption continue to be of great importance within the field of computing, especially as computers proliferate. A victim cache is a small fully associative cache that “captures” lines evicted from L1 cache memory, thereby reducing lower memory accesses and compensating for conflict misses. Little experimentation has been done to evaluate its effect on system power behavior and consumption. This project investigates the performance and power consumption of three different processor memory designs for a sample program using a field programmable gate array (FPGA) and the Vivado Integrated Development Environment. One design has no caching whatsoever, one utilizes separate direct-mapped L1 instruction and data caches, and the last utilizes both direct-mapped L1 and smaller fully associative victim caches for both instructions and data. Each of these was given the same simple testbench program, compiled from C, disassembled, and translated into RISC-V machine code. The number of clock cycles for execution and power estimations provided by the Xilinx Vivado Integrated Development Environment were compred for a testbench program. The ratio of power over time showed a significant benefit in both power consumption and performance for the system with ony L1 caches, not not an overall benefit from including victim caches. However, other instruction streams that cause more conflict misses may still benefit