Resistance Increase Due to Electromigration Induced Depletion Under TSV
- Frank, T.
- Chappaz, C.
- Leduc, P.
- Arnaud, L.
- Moreau, S.
- Thuaire, Aurélie
- El Farhane, R.
- Lorut, F.
- Anghel, Lorena
Publication date
April 2011
DOI Publisher
Institute of Electrical and Electronics Engineers (IEEE)Abstract
ISBN 978-1-4244-9111-7International audience3D-IC integration using Through Silicon Via (TSV) is becoming an alternative to overcome obstacles of CMOS scaling. As TSV processes reach maturity, reliability investigation becomes critical. To the best of our knowledge, we propose for the first time an analytical model of resistance increase due to electromigration induced voiding in a line ended by a TSV
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