High-performance nMOSFETs using a novel strained Si/SiGe CMOS architecture
- Olsen, Sarah H.
- O'Neill, Anthony G.
- Driscoll, Luke S.
- Kwa, Kelvin S. K.
- Chattopadhyay, Sanatan
- Waite, Andrew M.
- Tang, Yue T.
- Evans, Alan G.R.
- Norris, David J.
- Cullis, Anthony G.
- Paul, Douglas J.
- Robbins, David J.
Publication date
September 2003
DOI Publisher
Institute of Electrical and Electronics Engineers (IEEE)Abstract
Performance enhancements of up to 170% in drain current, maximum transconductance, and field-effect mobility are presented for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs. A novel layer structure comprising Si/Si/sub 0.7/Ge/sub 0.3/ on an Si/sub 0.85/Ge/sub 0.15/ virtual substrate (VS) offers improved performance advantages and a strain-compensated structure. A high thermal budget process produces devices having excellent on/off-state drain-current characteristics, transconductance, and subthreshold characteristics. The virtual substrate does not require chemical-mechanical polishing and the same performance enhancement is achieved with and without a titanium salicide process
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