Funding: This work has been partially supported by the European Union grant EU H2020-ICT-2014-1 project RePhrase (No. 644235).This paper describes a dynamic framework for mapping the threads of parallel applications to the computation cores of parallel systems. We propose a feedback-based mechanism where the performance of each thread is collected and used to drive the reinforcement-learning policy of assigning affinities of threads to CPU cores. The proposed framework is flexible enough to address different optimization criteria, such as maximum processing speed and minimum speed variance among threads. We evaluate the framework on the Ant Colony optimization parallel benchmark from the heuristic optimization application domain, and demons...
Parallel applications are highly irregular and high performance computing (HPC) infrastructures are ...
Parallel applications are highly irregular and high performance computing (HPC) infrastructures are ...
In a non-uniform memory access machine, the placement of software threads to hardware cores can have...
This paper describes a dynamic framework for mapping the threads of parallel applications to the com...
This paper describes a dynamic framework for mapping the threads of parallel applications to the com...
This paper introduces a resource allocation framework specifically tailored for addressing the probl...
This paper introduces a reinforcement-learning based resource allocation framework for dynamic place...
Funding: This work has been supported by the European Union grant EU H2020-ICT-2014-1 project RePhra...
This paper introduces a learning-based framework for dynamic placement of threads of parallel applic...
Modern day hardware platforms are parallel and diverse, ranging from mobiles to data centers. Mains...
We report on the improvements. that can be achieved by applying machine learning techniques, in part...
Scientific applications are large, complex, irregular, and computationally intensive and are charact...
In this study, we investigate a real-time system where computationally intensive tasks are executed ...
We report on the improvements that can be achieved by applying machine learning techniques, in parti...
Power and energy is the first-class design constraint for multi-core processors and is a limiting fa...
Parallel applications are highly irregular and high performance computing (HPC) infrastructures are ...
Parallel applications are highly irregular and high performance computing (HPC) infrastructures are ...
In a non-uniform memory access machine, the placement of software threads to hardware cores can have...
This paper describes a dynamic framework for mapping the threads of parallel applications to the com...
This paper describes a dynamic framework for mapping the threads of parallel applications to the com...
This paper introduces a resource allocation framework specifically tailored for addressing the probl...
This paper introduces a reinforcement-learning based resource allocation framework for dynamic place...
Funding: This work has been supported by the European Union grant EU H2020-ICT-2014-1 project RePhra...
This paper introduces a learning-based framework for dynamic placement of threads of parallel applic...
Modern day hardware platforms are parallel and diverse, ranging from mobiles to data centers. Mains...
We report on the improvements. that can be achieved by applying machine learning techniques, in part...
Scientific applications are large, complex, irregular, and computationally intensive and are charact...
In this study, we investigate a real-time system where computationally intensive tasks are executed ...
We report on the improvements that can be achieved by applying machine learning techniques, in parti...
Power and energy is the first-class design constraint for multi-core processors and is a limiting fa...
Parallel applications are highly irregular and high performance computing (HPC) infrastructures are ...
Parallel applications are highly irregular and high performance computing (HPC) infrastructures are ...
In a non-uniform memory access machine, the placement of software threads to hardware cores can have...