On board Processor and Processing Strategies for Next Generation Reconfigurable Satellite Payloads

Today, the increasing demand in higher data rates necessitates new methods as well as higher flexibility for satellite telecommunication payloads in order to address a variety of applications and customers. This paper presents one of these processing strategies that is applicable to today’s processing satellite payloads aiming to meet those demands. For this purpose, a two-tier filter bank is designed as part of a digital onboard processor, which first divides the spectrum at the output of the ADC into a number of sub-bands extracting all the stacked channels in the digital domain. Following the analysis section of the first tier of operations, the extracted channels go under a secondary channelisation process to obtain much finer granularity of 31.25 kHz or 50 kHz depending on the communication standard used for data transmission. The implementation of the channeliser was delivered on a bit-true simulation model and the input and the output of the channelisers were compared and evaluated both in the time and frequency domains