Entwicklung und Charakterisierung vertikaler Silizium-Feldeffekttransistoren auf der Basis selektiver Epitaxie

The development in microelectronics leads to smaller devices, which requires the definition of small structures in the device processing. It seems to be questionable, if optical lithography is able to define lateral structures smaller then 100nm. To avoid this limitation of optical lithography, two MOSFET concepts with a vertical layout were developed within this work. The first concept, the VOXFET, uses a layer sequence of oxide/polysilicon/oxide, in which holes with vertical sidewalls were etched. At the sidewalls the gate oxide is generated by a. conform deposition of silicon oxide. Into these holes, the epitaxy is grown selectively by LPCVD. The polysilicon, used as gate electrode, is generated before the gate oxide is deposited, and both exist, before the channel region is grown. With the VFET concept the epitaxy is grown selectively in an oxide mask, which is removed after the epitaxy. The gate oxide is performed by thermal oxidation and afterwards, the polysilicon, used as gate electrode, is deposited. The VOXFET reaches a transconductance of I00mS/mm for transistors with a channel length of 135nm and an oxide thickness of 12nm, while the VFET reaches 135mS/mm for a channel length of 200nm and an oxide thickness of 8nm. To avoid the memory effect by phosphor doping in LPCVD, first investigations on Quasiselective Growth using MBE were done