A technique to reduce the capacitor size in two stage Miller compensated opamp

In this paper two stage Miller compensated opamp has been discussed qualitatively and quantitatively. A modification to the conventional compensation network has been proposed, which will reduce the capacitor size hence circuit area. Transfer function for the newly proposed solution has been derived and explained the results. A prototype was developed in 65nm TSMC CMOS technology and simulation results have been presented. Amplifier achieved 60dB low frequency gain, 12MHz bandwidth and 55° phase margin while consuming 650uW power from 1.2V power supply. Circuit occupies 5348um 2 silicon area