Development, Demonstration, and Device Physics of FET-Accessed One-Transistor GaAs Dynamic Memory Technologies

The introduction of digital GaAs into modem high-speed computing systems has led to an increasing demand for high-density memory in these GaAs technologies. To date, most of the memory development efforts in GaAs have been directed toward four- and six-transistor static RAM\u27s, which consume substantial chip area and dissipate much static power resulting in limited single-chip GaAs storage capacities. As it has successfully done in silicon, a one-transistor dynamic RAM approach could alleviate these problems making higher density GaAs memories possible. This dissertation discusses theoretical and experimental work that presents the possibility for a high-speed, low-power, one-transistor dynamic RAM technology in GaAs. The two elements of the DRAM cell, namely the charge storage capacitor and the access field-effect transistor have been studied in detail. Isolated diode junction charge storage capacitors have demonstrated 30 minutes of storage time at room temperature with charge densities comparable to those obtained in planar silicon DRAM capacitors. GaAs JFET and MESFET technologies have been studied, and with careful device design and choice of proper operating voltages experimental results show that both can function as acceptable access transistors. One-transistor MESFET- and JFET-accessed DRAM cells have been fabricated and operated at room temperature and above with a standby power dissipation that is only a small fraction of the power dissipated by the best commercial GaAs static RAM cells. A 2 x 2 bit demonstration array was built and successfully operated at room temperature to demonstrate the addressable read/write capability of this new technology