Most existing methods of mapping algorithms into processor arrays are restricted to the case where n-dimensional algorithms or algorithms with n nested loops are mapped into (n—l)-dimensional arrays. However, in practice, it is interesting to map n-dimensional algorithms into (k —l)-dimensional arrays where k\u3c.n. For example, many algorithms at bit-level are at least 4-dimensional (matrix multiplication, convolution, LU decomposition, etc.) and most existing bit level processor arrays are 2-dimensional. A computational conflict occurs if two or more computations of an algorithm are mapped into the same processor and the same execution time. In this paper, necessary and sufficient conditions are derived to identify all mappings without co...
this paper how to execute a class of n + 1-dimensional uniform recurrences in SPMD (Single Program M...
Using a directed acyclic graph (dag) model of algorithms, we solve a problem related to precedence-c...
Iteration space tiling is a common strategy used by parallelizing compilers and in performance tunin...
Three related problems, among others, are faced when trying to execute an algorithm on a parallel ma...
The production of regular computations using algorithmic engineering techniques is beginning to play...
With the continuing growth of VLSI technology, special-purpose parallel processors have become a pro...
This paper adresses the problem of efficient mappings of nested loops, and more generally of system...
Many techniques and design tools have been developed for mapping algorithms to array processors. Lin...
An algorithm can be modeled as an index set and a set of dependence vectors. Each index vector in th...
We deal with the problem of partitioning and mapping uniform loop nests onto physical processor arra...
This dissertation provides a fairly comprehensive treatment of a broad class of algorithms as it per...
[[abstract]]The data dependence graph is very useful to parallel algorithm design. In this paper, ap...
(eng) We deal with the problem of partitioning and mapping uniform loop nests onto physical processo...
Although, computer system architecture and the throughput enhances continuously, the need for high c...
Minimizing the amount of time and number of processors needed to perform an application reduces the ...
this paper how to execute a class of n + 1-dimensional uniform recurrences in SPMD (Single Program M...
Using a directed acyclic graph (dag) model of algorithms, we solve a problem related to precedence-c...
Iteration space tiling is a common strategy used by parallelizing compilers and in performance tunin...
Three related problems, among others, are faced when trying to execute an algorithm on a parallel ma...
The production of regular computations using algorithmic engineering techniques is beginning to play...
With the continuing growth of VLSI technology, special-purpose parallel processors have become a pro...
This paper adresses the problem of efficient mappings of nested loops, and more generally of system...
Many techniques and design tools have been developed for mapping algorithms to array processors. Lin...
An algorithm can be modeled as an index set and a set of dependence vectors. Each index vector in th...
We deal with the problem of partitioning and mapping uniform loop nests onto physical processor arra...
This dissertation provides a fairly comprehensive treatment of a broad class of algorithms as it per...
[[abstract]]The data dependence graph is very useful to parallel algorithm design. In this paper, ap...
(eng) We deal with the problem of partitioning and mapping uniform loop nests onto physical processo...
Although, computer system architecture and the throughput enhances continuously, the need for high c...
Minimizing the amount of time and number of processors needed to perform an application reduces the ...
this paper how to execute a class of n + 1-dimensional uniform recurrences in SPMD (Single Program M...
Using a directed acyclic graph (dag) model of algorithms, we solve a problem related to precedence-c...
Iteration space tiling is a common strategy used by parallelizing compilers and in performance tunin...