International audienceMonolithic 3D (M3D) integration offers significant performance, power, and area benefits. However, the design of a reliable power-delivery network (PDN) is challenging for M3D ICs due to high power density and current demand per unit area. In addition, the higher susceptibility of interconnects to electromigra-tion and stress migration increases the complexity of PDN design. We propose a framework to design a reliable PDN for M3D ICs using accurate electrical and reliability models. We leverage genetic programming to explore the design space to optimize the resources dedicated for power delivery in order to achieve reliable operation. We also analyze power-supply noise (PSN) during scan-based testing and compare it wit...
Thesis (Ph.D.), Electrical Engineering, Washington State UniversityAs the demand for high performanc...
Reducing the interconnect size with each technology node and increasing speed with each generation i...
In this work, the impact of across-chip temperature and power supply voltage variations, on performa...
The major challenges in low power and reliable monolithic 3D IC design are studied and quantified. N...
As the semiconductor process nodes advance to 28nm and below and three-dimensional (3D) silicon inte...
Providing a reliable power distribution network (PDN) is a critical design challenge for mobile syst...
As one of more-than-Moore technologies, 3D ICs enable next-generation systems with much higher devic...
Abstract—Aside from the benefits it brings, 3D-IC tech-nology inevitably exacerbates the difficulty ...
Abstract—With the rapid advance of die stacking and through-silicon-via fabrication technologies, th...
This paper proposes an efficient method to predict the worst case of voltage violation by multi-doma...
Many-tier systems are the future of 3D integration. In this work we explore power delivery system de...
International audienceOngoing advancements in 3-D manufacturing are enabling 3-D ICs to contain seve...
This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circu...
In advanced technology nodes, emerging die-to-wafer (D2W) integration technology is a promising More...
The objective of this research is to develop physical design methodologies for monolithic 3D ICs and...
Thesis (Ph.D.), Electrical Engineering, Washington State UniversityAs the demand for high performanc...
Reducing the interconnect size with each technology node and increasing speed with each generation i...
In this work, the impact of across-chip temperature and power supply voltage variations, on performa...
The major challenges in low power and reliable monolithic 3D IC design are studied and quantified. N...
As the semiconductor process nodes advance to 28nm and below and three-dimensional (3D) silicon inte...
Providing a reliable power distribution network (PDN) is a critical design challenge for mobile syst...
As one of more-than-Moore technologies, 3D ICs enable next-generation systems with much higher devic...
Abstract—Aside from the benefits it brings, 3D-IC tech-nology inevitably exacerbates the difficulty ...
Abstract—With the rapid advance of die stacking and through-silicon-via fabrication technologies, th...
This paper proposes an efficient method to predict the worst case of voltage violation by multi-doma...
Many-tier systems are the future of 3D integration. In this work we explore power delivery system de...
International audienceOngoing advancements in 3-D manufacturing are enabling 3-D ICs to contain seve...
This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circu...
In advanced technology nodes, emerging die-to-wafer (D2W) integration technology is a promising More...
The objective of this research is to develop physical design methodologies for monolithic 3D ICs and...
Thesis (Ph.D.), Electrical Engineering, Washington State UniversityAs the demand for high performanc...
Reducing the interconnect size with each technology node and increasing speed with each generation i...
In this work, the impact of across-chip temperature and power supply voltage variations, on performa...