System Level Analysis And Design For Wireless Inter-Chip Interconnection Communication Systems By Applying Advanced Wireless Communication Technologies

As the dramatic development of high speed integrated circuits has progressed, the 60 GHz silicon technology has been introduced to enable much faster computer systems and their corresponding applications. However, when signals are propagating at 60 GHz or higher frequencies on a PCB (Printed Circuit Board), the crosstalk among signal buses and devices, trace losses, and introduced parasitic capacitance and inductance between high density traces, become significant and may be severe enough such that the inter-chip communications will not be able to meet computer system signal specifications. High speed circuit signal integrity researchers in both electronic industries and academia have explored various methodologies to resolve these high frequency issues. Moreover, Intel is introducing Ultra Path Interconnect (UPI) for multi-core server systems, which demands more than 2.44 Tbps data rate between two CPUs, and 1.5 Tbps data rate for PCIe channel operation. Recently, the concept of the wireless inter/intra-chip interconnection (WIIC) technology was introduced [19, 23] for solving high frequency signal integrity issues. Here this dissertation mainly focuses on the inter-chip case while still using the WIIC designation for generality. Various WIIC technologies have been presented in the literature, which have focused on the investigations on Ultra Wide-Band (UWB), propagation channels, modulations, antennas, and power controls and interference. However, not much research has focused on a system level design, which includes the lowest two layers of the communication protocol in a WIIC system, namely, the physical, and data link layers. Also, the previously published literature has rarely reached the data rate at 100 Gbps or higher, and none of the prior research has obtained a spectrum utilization ratio of 4 bit/Hz or greater. In addition, currently existing research has not fully taken advantage of advanced and matured wireless communication technologies such as Orthogonal Frequency Division Multiplexing (OFDM), high order modulation, and Multiple-Input/Multiple-Output (MIMO) systems for increasing data rates and improving reliability, although the use of UWB [29], conventional FDMA or TDMA [39], and binary modulations including Binary Phase Shift Keying (BPSK) [22], On-Off Keying (OOK) [31], and Amplitude Shift Keying (ASK) [35] have been studied in previous research. In this dissertation, a complete WIIC system and a representative WIIC channel model have been developed by taking full advantages of advanced wireless communication techniques. First, this research has analyzed the potential of higher-order modulation, error correction, OFDM, and channel coding to the WIIC setting. Although MIMO, interleaving and scrambling are also analyzed but not included in the current version of the proposed WIIC system, they could be featured in hypothetically ideal future research to determine their potential benefits. Second, the performance of a proposed WIIC system has been analyzed in order to reach 100 Gbps data rate. Third, a 60 GHz WIIC channel based on metamaterial Electronic Band Gap (EBG) absorbers has been designed and analyzed using the numerical electromagnetics solver HFSS® and this EBG is integrated into the representative WIIC channel. Moreover, the impulse response of the WIIC channel is numerically extracted and is used for the system validation and testing. Furthermore, the system has been simulated with the WIIC channel and the wired PCB channel. It has been found that, the Bit Error Rate (BER) performance of the proposed WIIC channel is close to that of an AWGN channel with FEC, and much better than the AWGN channel without FEC, which means that the designed WIIC system and channel work properly within the frequency band centered at 60 GHz, while the wired PCB channel is almost cut off at 15 GHz or higher for the cases investigated. With only five or six layers on a PCB board, the WIIC system is able to provide 384 Gbps data rate theoretically with 12 GHz bandwidth, while the wired PCB counterpart needs more than 20 layers in order to avoid severe SI problems and to properly layout the Tbps channels. The current version of the WIIC system is able to provide 24 Gbps data rate with the bandwidth of 12 GHz using OFDM and QPSK