Evaluation of A New Power-Hardware-In-The-Loop (Phil) Interface Algorithm For Current Controlled Amplifiers

The use of Power-Hardware-In-the-Loop (PHIL) system studies is on the rise, in simulation and validation testing of designs for new products and systems. All PHIL systems can be split into three portions: the computer simulation model, the physical hardware component of interested, and the interface algorithm (IA) that is used to connect the simulation model, with the hardware. These interface algorithms allows for the computer simulation to virtually exchange power with the hardware to be tested (HUT) via a power amplifier and feedback measuring devices. The majority of these interface algorithm developed, are designed for use with voltage controlled power amplifiers that supply the power to the hardware under test. In fact there is only one IA that is available for use with current controlled power amplifiers, used as the hardware\u27s power supply, which is known to date. This IA is the current type Ideal Transformer Model interface algorithm (I-type ITM IA). The purpose of this work is to introduce and evaluate a new PHIL interface algorithm that is developed, for use with these current controlled power amplifiers. This work first takes a detailed look at an IA that is designed for voltage amplifiers, which is what this new PHIL IA is based from. Then an evaluation of the new PHIL IA is conducted in terms of stability and accuracy by the use of the IA loop gain equation and computer simulations of the new PHIL IA. Several experimental comparison tests are performed between the I-type ITM IA and the new PHIL IA presented in this work are done. This is in order to show that the new PHIL IA is just as accurate as the I-type ITM IA but has a higher level of stability than the I-type ITM IA