Advanced physically based device modeling for gate current and hot carrier phenomena in scaled MOSFETs

Gate oxide scaling is a key issue to proceed down the semiconductor roadmap toward ultimate MOSFET performance1. Reliability and leakage currents compete as limiting factors of this aspect of the scaling process2,3. Whatever the bottleneck will be, detailed calibrated physically based models of carrier transport through silicon-dielectric-silicon stacks are becoming increasingly important to understand leakage and degradation mechanisms and to perform meaningful reliability projections. Significant progress has been made recently in this direction, that allowed for important advances in the understanding of thin dielectrics4, 5, 6, 3. In this paper, we report on a comprehensive physically based model of carrier injection in the gate oxide and of hot carrier processes in MOS devices, as well as its application to tunneling MOS capacitors. In light of this model, we revisit the Anode Hole Injection (AHI) and photon emission experiments of Ref.7 and we demonstrate that conclusions quite different from those of Ref.7 can be drawn from the same experiments with the help of a more detailed physical picture of the involved processes. Implications of this analysis for future MOSFETs are also briefly discussed. The paper is organized as follows: Sections 2 and 3 describe the model and its verification, respectively. Section 4 discusses applications to MOS capacitors, with particular regard to the interpretation of the experiments of Ref.7. Considerations on thin oxides are given in Section 5. Conclusion are drawn in Section 6