Add to ORKGA clock and data recovery architecture for highspeed communication systems is proposed. Based on early-late method, the bang-bang phase and frequency detector works in two modes: half-rate mode and quarter-rate mode, thus a large applicable data rate range is available. Simulated in a 0.18-μm CMOS technology, the circuit exhibits a peak-to-peak jitter of 48ps in the recovered quarter-rate clock with PRBS length of 215-1 at 6.25-Gb/s. The data is recovered and demultiplexed inherently. In quarter-rate mode, the power dissipation is 8OmW from a 1.8V supply
This paper describes the design and transistor level simulation of a novel architecture of PLL-based...
This paper describes the design and transistor level simulation of a novel architecture of PLL-based...
This paper discusses the design and performance of all-digital clock and data recovery mechanisms in...
A clock and data recovery (CDR) circuit using a new half-rate wide-range phase detection technique h...
This paper describes the design and fabrication of a clock and data recovery circuit (CDR). We propo...
A half-rate reference-less clock and data recovery circuit is proposed, incorporating a coarse frequ...
Abstract—A half-rate reference-less clock and data recovery circuit is proposed, incorporating a coa...
Abstract—A 20-Gb/s full-rate clock and data recovery circuit employing a mixer-type linear phase det...
The high demanded data throughput of data communication between units in the system can be covered b...
A new bit rate adaptive clock and data recovery circuit able to operate in a range from 3.125 Mb/s t...
Today's telecommunications infrastructures and consumer electronics rely largely on serial communic...
The maturing of the telecommunications industry has seen the development and implementation of devi...
With a new 1/8-rate linear phase detector (PD), a 5-Gbit/s clock and data recovery (CDR) circuit is ...
In this paper, a new dual-loop half-rate clock recovery is proposed for chip-to-chip communications....
An 8Gb/s current mode logic (CML) transmitter with multi-tap FIR pre-emphasis has been implemented i...
This paper describes the design and transistor level simulation of a novel architecture of PLL-based...
This paper describes the design and transistor level simulation of a novel architecture of PLL-based...
This paper discusses the design and performance of all-digital clock and data recovery mechanisms in...
A clock and data recovery (CDR) circuit using a new half-rate wide-range phase detection technique h...
This paper describes the design and fabrication of a clock and data recovery circuit (CDR). We propo...
A half-rate reference-less clock and data recovery circuit is proposed, incorporating a coarse frequ...
Abstract—A half-rate reference-less clock and data recovery circuit is proposed, incorporating a coa...
Abstract—A 20-Gb/s full-rate clock and data recovery circuit employing a mixer-type linear phase det...
The high demanded data throughput of data communication between units in the system can be covered b...
A new bit rate adaptive clock and data recovery circuit able to operate in a range from 3.125 Mb/s t...
Today's telecommunications infrastructures and consumer electronics rely largely on serial communic...
The maturing of the telecommunications industry has seen the development and implementation of devi...
With a new 1/8-rate linear phase detector (PD), a 5-Gbit/s clock and data recovery (CDR) circuit is ...
In this paper, a new dual-loop half-rate clock recovery is proposed for chip-to-chip communications....
An 8Gb/s current mode logic (CML) transmitter with multi-tap FIR pre-emphasis has been implemented i...
This paper describes the design and transistor level simulation of a novel architecture of PLL-based...
This paper describes the design and transistor level simulation of a novel architecture of PLL-based...
This paper discusses the design and performance of all-digital clock and data recovery mechanisms in...