An efficient delay model for MOS current-mode logic automated design and optimization

MOS current-mode logic (MCML) is a low-noise alternative to CMOS logic. The lack of MCML automation tools, however, has deterred designers from applying MCML to complex digital functions. This paper presents an efficient MCML optimization program that can be used to properly size MCML gates. The delay model accuracy is adjusted by fitting measured gate delays by means of technology-dependent parameters. For an N number of logic gates, the proposed mathematical program has reduced the number of variables to N+1, in comparison to 7N+1 in the most recent work on this topic. The program has been implemented to efficiently optimize a 4-bit ripple carry adder and an 8-bit decoder in 0.18-μm CMOS technology