A novel fractional-N PLL architecture with hybrid of DCO and VCO

A novel fractional-N Phase-Lock Loop (PLL) architecture is proposed in this paper. The architecture features a hybrid of DCO and VCO, which is controlled by a mixed-mode loop filter. The analog part of the filter works as the proportional path of the loop and the digital part as the integral path. The proposed architecture takes advantages of both analog PLL and All Digital PLL (ADPLL) and overcomes some problems encountered with each technique. The proposed solution has been verified in the behavioral level and a chip is under development