Add to ORKGA novel current-mode approach is proposed for implementing basic building blocks of an analog iterative decoder. The decoder is based on the so-called min-sum algorithm and can be used to decode powerful coding schemes such as low-density parity-check (LDPC) codes and turbo codes. The proposed circuits can be implemented by standard CMOS technology, which means lower fabrication cost and/or simpler design compared to previously reported analog iterative decoders that are based on BiCMOS or sub-threshold CMOS technology. An example decoder design, based on TSMC 0.18 μm CMOS technology is also presented for a (7,4) Hamming code
This work presents the design and the test results of an analog decoder for the 40-bit block length,...
A high-frequency low-power switched-current (SI) sample-and-hold (S/H) of a current-mode analog iter...
This work presents the design and the test results of an analog decoder for the 40-bit block length,...
In this paper, a novel current-mode approach is proposed for implementing basic building blocks of a...
In this paper, a novel current-mode approach is proposed for implementing basic building blocks of a...
Current-mode circuits are presented for implementing analog min-sum (MS) iterative decoders. These d...
Current-mode circuits are presented for implementing analog min-sum (MS) iterative decoders. Propose...
IN THIS THESIS, the concept of analog decoding as a power-saving implementation alternative to the t...
Abstract- Analog iterative decoders offer several advantages-over their digital counterparts in term...
A new current-mode maximum winner-take-all (Max WTA) circuit is presented. Inputs and output of the ...
Abstract—A margin propagation (MP) algorithm that can be used for implementing analog decoders for l...
In this work, we consider a class of structured regular LDPC codes, called Turbo-Structured LDPC (TS...
In this work we present a full analog turbo decoder for hard-disk EPR-IV read channels in CMOS techn...
This paper presents the architecture and the corresponding simulation results for a very low power h...
This paper is concerned with the implementation of iterative decoding algorithms in analog VLSI. We ...
This work presents the design and the test results of an analog decoder for the 40-bit block length,...
A high-frequency low-power switched-current (SI) sample-and-hold (S/H) of a current-mode analog iter...
This work presents the design and the test results of an analog decoder for the 40-bit block length,...
In this paper, a novel current-mode approach is proposed for implementing basic building blocks of a...
In this paper, a novel current-mode approach is proposed for implementing basic building blocks of a...
Current-mode circuits are presented for implementing analog min-sum (MS) iterative decoders. These d...
Current-mode circuits are presented for implementing analog min-sum (MS) iterative decoders. Propose...
IN THIS THESIS, the concept of analog decoding as a power-saving implementation alternative to the t...
Abstract- Analog iterative decoders offer several advantages-over their digital counterparts in term...
A new current-mode maximum winner-take-all (Max WTA) circuit is presented. Inputs and output of the ...
Abstract—A margin propagation (MP) algorithm that can be used for implementing analog decoders for l...
In this work, we consider a class of structured regular LDPC codes, called Turbo-Structured LDPC (TS...
In this work we present a full analog turbo decoder for hard-disk EPR-IV read channels in CMOS techn...
This paper presents the architecture and the corresponding simulation results for a very low power h...
This paper is concerned with the implementation of iterative decoding algorithms in analog VLSI. We ...
This work presents the design and the test results of an analog decoder for the 40-bit block length,...
A high-frequency low-power switched-current (SI) sample-and-hold (S/H) of a current-mode analog iter...
This work presents the design and the test results of an analog decoder for the 40-bit block length,...