Add to ORKGEffective optimization methods aimed at achieving maximal speeds in single-technology logic circuits are widely available but systematic ways suitable for circuits involving mixtures of logic families are not. In this paper, the combination of standard CMOS with CPL is examined with an eye to finding the best structure and the best insertion points for CMOS buffers intended to improve a CPL chain's propagation time and drive capability
The Critical Voltage Transition Logic (CVTL) was proposed by in [1] [2]. The concept of the design ...
Standard static CMOS logic is responding to the requirement of high frequency and low power of digit...
High throughput and low latency designs are required in modern high performance systems, especially ...
Effective optimization methods aimed at achieving maximal speeds in single-technology logic circuits...
In this paper, a CMOS logic delay optimization algorithm was used to find the optimal number of pass...
This paper presents a unified model for delay estimation in various CMOS logic styles. It also deriv...
In this paper a pencil and paper optimized design for CML and ECL gates is proposed. The approaches ...
This paper presents a unified model for delay estimation in various CMOS logic styles including conv...
In this paper a pencil and paper optimized design for CML and ECL gates are proposed. The approaches...
An improved timing model for CMOS combinational logic is presented. The model is based on an analyti...
This book is a monograph devoted to logic synthesis and optimization for CPLDs. CPLDs' macrocell can...
Comparator is a very useful combinational logic circuit. In this paper performance analysis of CMOS ...
Abstract — This paper presents the first reported joint gate sizing and buffer insertion method for ...
This paper presents a method for optimizing BiCMOS logic networks that exploits the fact that such n...
We present more evidence in a 0.25 μm CMOS technology that the pass-transistor logic (PTL) structure...
The Critical Voltage Transition Logic (CVTL) was proposed by in [1] [2]. The concept of the design ...
Standard static CMOS logic is responding to the requirement of high frequency and low power of digit...
High throughput and low latency designs are required in modern high performance systems, especially ...
Effective optimization methods aimed at achieving maximal speeds in single-technology logic circuits...
In this paper, a CMOS logic delay optimization algorithm was used to find the optimal number of pass...
This paper presents a unified model for delay estimation in various CMOS logic styles. It also deriv...
In this paper a pencil and paper optimized design for CML and ECL gates is proposed. The approaches ...
This paper presents a unified model for delay estimation in various CMOS logic styles including conv...
In this paper a pencil and paper optimized design for CML and ECL gates are proposed. The approaches...
An improved timing model for CMOS combinational logic is presented. The model is based on an analyti...
This book is a monograph devoted to logic synthesis and optimization for CPLDs. CPLDs' macrocell can...
Comparator is a very useful combinational logic circuit. In this paper performance analysis of CMOS ...
Abstract — This paper presents the first reported joint gate sizing and buffer insertion method for ...
This paper presents a method for optimizing BiCMOS logic networks that exploits the fact that such n...
We present more evidence in a 0.25 μm CMOS technology that the pass-transistor logic (PTL) structure...
The Critical Voltage Transition Logic (CVTL) was proposed by in [1] [2]. The concept of the design ...
Standard static CMOS logic is responding to the requirement of high frequency and low power of digit...
High throughput and low latency designs are required in modern high performance systems, especially ...