Add to ORKGIn this paper, a CMOS logic delay optimization algorithm was used to find the optimal number of pass transistors to use for buffer insertion into a CPL chain. The result was then used as a guide during the design of a 64-bit high-speed static adder. Simulation results indicated a worst-case critical-path delay of 650ps for a device based on TSMC 0.18μ m technology
This paper discusses a rail to rail swing, mixed logic style 1-bit 28-transistor (28T) full-adder, b...
High speed, low power, and area efficient adders and comparators continue to play a key role in hard...
We present more evidence in a 0.25 μm CMOS technology that the pass-transistor logic (PTL) structure...
Effective optimization methods aimed at achieving maximal speeds in single-technology logic circuits...
Effective optimization methods aimed at achieving maximal speeds in single-technology logic circuits...
This paper presents the design exploration of CMOS 64-bit adders designed using threshold logic gate...
Copyright © 2004 IEEEThis paper presents the design exploration of CMOS 64-bit adders designed using...
Copyright © 2013 Kumar Yelamarthi. This is an open access article distributed under the Creative Com...
Speed of operation depends on the longest critical paths in the multi-bit adders and also the MOSFET...
This paper presents a unified model for delay estimation in various CMOS logic styles. It also deriv...
Speed and power is the major constraint in modern digital design. We have to design the high speed, ...
© 2004 COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstrac...
In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation a...
This paper analyzes methods to minimize the power-delay product of 64-bit carry-select adders intend...
An effective approach to timing and power optimization for single clocking and multiple clocking dyn...
This paper discusses a rail to rail swing, mixed logic style 1-bit 28-transistor (28T) full-adder, b...
High speed, low power, and area efficient adders and comparators continue to play a key role in hard...
We present more evidence in a 0.25 μm CMOS technology that the pass-transistor logic (PTL) structure...
Effective optimization methods aimed at achieving maximal speeds in single-technology logic circuits...
Effective optimization methods aimed at achieving maximal speeds in single-technology logic circuits...
This paper presents the design exploration of CMOS 64-bit adders designed using threshold logic gate...
Copyright © 2004 IEEEThis paper presents the design exploration of CMOS 64-bit adders designed using...
Copyright © 2013 Kumar Yelamarthi. This is an open access article distributed under the Creative Com...
Speed of operation depends on the longest critical paths in the multi-bit adders and also the MOSFET...
This paper presents a unified model for delay estimation in various CMOS logic styles. It also deriv...
Speed and power is the major constraint in modern digital design. We have to design the high speed, ...
© 2004 COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstrac...
In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation a...
This paper analyzes methods to minimize the power-delay product of 64-bit carry-select adders intend...
An effective approach to timing and power optimization for single clocking and multiple clocking dyn...
This paper discusses a rail to rail swing, mixed logic style 1-bit 28-transistor (28T) full-adder, b...
High speed, low power, and area efficient adders and comparators continue to play a key role in hard...
We present more evidence in a 0.25 μm CMOS technology that the pass-transistor logic (PTL) structure...