Optimization of high-speed VLSI interconnects: A review (invited article)

Today's electronic systems such as computers and digital communication systems, have necessitated a rapid increase in operating frequency. Because of this, VLSI interconnects have become one of the critical issues in an overall system design. Improperly designed interconnects lead to signal integrity degradations such as signal delay, cross talk and ground noise, limiting the overall system performance. In recent years, research into the interconnect optimization problem has been very active, and much important progress has been made. This article presents a review of the current status of this subject area. The formulations of signal-integrity oriented optimization of interconnects at different levels of electronics systems, that is, chip, multichip module (MCM), and printed circuit board (PCB) levels, are reviewed, together with various optimization techniques. Highlights on parallel and multilevel optimization for interconnect networks and the use of macromodeling techniques are also presented. Advanced formulations of interconnect optimizations featuring manufacturability oriented and multidisciplinary design objectives are reviewed. A discussion on the future challenges in the area is included at the end