A Combined Approach to Validate the Design of Embedded Network Devices

To validate an embedded network device it is important to insert it in a model of a real system and test its interaction with the surrounding blocks and used protocols. The proposed methodology joins two simulation environments, both based on the C++ programming language. The first (SystemC) is both a hardware definition language and a simulation library designed to model and simulate hardware and software systems:. The second (Network Simulator 2) is both a network definition language and a simulation tool designed to model and simulate network topologies. The aim of the paper concerns the analysis of the efficient integration of the two modeling/simulation environments. The proposed methodology; joining together SystemC and Network Simulator 2, has been applied to an example embedded network device based on the IEEE 1355 protocol