Architecture and implementation of real-time 3D stereo vision on a Xilinx FPGA
- Θωμας Σωτηριος(http://users.isc.tuc.gr/~sthomas)
- Thomas Sotirios(http://users.isc.tuc.gr/~sthomas)
- Παπαδημητριου Κυπριανος(http://users.isc.tuc.gr/~kpapadimitriou)
- Papadimitriou Kyprianos(http://users.isc.tuc.gr/~kpapadimitriou)
- Δολλας Αποστολος(http://users.isc.tuc.gr/~adollas)
- Dollas Apostolos(http://users.isc.tuc.gr/~adollas)
DOI Publisher
Institute of Electrical and Electronics Engineers (IEEE)Abstract
Summarization: Many applications from autonomous vehicles to surveillance can benefit from real-time 3D stereo vision. In the present work we describe a 3D stereo vision design and its implementation that exploits effectively the resources of a Xilinx Virtex-5 FPGA. The post place-and-route design achieved a processing rate of 87 frames per sec (fps) for 1920 × 1200 resolution. The hardware prototype system was tested and validated for several data sets with resolutions up to 400 × 320 and we achieved a processing rate of 1570 fps.Παρουσιάστηκε στο: IFIP/IEEE International Conference on Very Large Scale Integratio
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