Methodology and experimental setup for the determination of system-level dynamic reconfiguration overhead

Summarization: Dynamic reconfiguration is gaining popularity [2], [4] but it may cause degradation of overall execution time due to the time to download the bitstream before an application starts execution of the new configuration. Thus evaluation of its performance becomes an interesting area [3]. In this work we include an analysis of the reconfiguration time by defining the delays that add up to it. An experimental setup is deployed that can be used for performance evaluation of applications implemented with dynamic reconfiguration, as well as of mechanisms developed to reduce reconfiguration overhead. The configuration memory of Xilinx Virtex-II is arranged in vertical frames. In a self-reconfigurable system [1] where the PowerPC reconfigures the FPGA through the Internal Configuration Access Port (ICAP), once data are available in the configuration cache HWICAP BRAM the nominal time to reconfigure a single frame is 12.5 µs for 66 MHz. However, this is not the only aspect in the reconfiguration process. Several physical components of the system add significant delays causing reconfiguration time to increase more than three orders of magnitude as compared to the above time.Παρουσιάστηκε στο: IEEE International Symposium on Field-Programmable Custom Computing Machine