A reconfigurable logic-based processor for the SCAN image and video encryption algorithm
- Δολλας Αποστολος(http://users.isc.tuc.gr/~adollas)
- Dollas Apostolos(http://users.isc.tuc.gr/~adollas)
- Bourbakis, Nikolaos G(http://viaf.org/viaf/39451290)
- Kachris, Christoforos(http://viaf.org/viaf/295998821)
DOI Publisher
Springer Science and Business Media LLCAbstract
Summarization: This paper presents a detailed architecture and a reconfigurable logic based hardware design of the SCAN algorithm. This architecture can be used to encrypt high resolution images in real-time. Although the SCAN algorithm is a block cipher algorithm with arbitrarily large blocks, the present design is for 64×64 pixel blocks in order to provide real-time image encryption throughput. The architecture was initially targeted at the Xilinx XCV-1000 FPGA, for which design and performance results are presented in the paper.Presented on: International Journal of Parallel Programmin
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