Summarization: The authors consider whether SPECmarks, the figures of merit obtained from running the SPEC benchmarks under certain specified conditions, accurately indicate the performance to be expected from real, live work loads. Miss ratios for the entire set of SPEC92 benchmarks are measured. It is found that instruction cache miss ratios in general, and data cache miss ratios for the integer benchmarks, are quite low. Data cache miss ratios for the floating-point benchmarks are more in line with published measurements for real work loads.Presented on: IEEE Micr
The standard trace-driven cache simulation evaluates the miss rate of cache C on an address trace T ...
The cache Miss Ratio Curve (MRC) serves a variety of purposes such as cache partitioning, applicatio...
In this paper, we use execution-driven simulation to study and compare vector processing performance...
Detailed micro-architecture studies often require time-consuming, cycle-accurate simulation. Unfortu...
With the software applications increasing in complexity, description of hardware is becoming increas...
SPEC compute intensive benchmarks are often used to evaluate processors in high-performance systems....
Abstract—Although modeling of memory caches for the purpose of cache design and process scheduling h...
Measurements of actual supercomputer cache performance has not been previously undertaken. PFC-Sim i...
Abstract-Design parameters interact in complex ways in modern processors, especially because out-of-...
Memory performance can be studied, process behavior can be characterized, and application performanc...
The floating point portion of the SPEC CPU suite and the HPC Challenge suite are widely recognized a...
AbstractThe embedded processor performance is significantly influenced by cache whose performance de...
This report presents results of the experiments assessing the sensitivity of SPEC CPU2006 benchmarks...
A new performance model of the memory hierarchy is first introduced, which describes all possible sc...
SIGLEAvailable at INIST (FR), Document Supply Service, under shelf-number : 14802 E, issue : a.1990 ...
The standard trace-driven cache simulation evaluates the miss rate of cache C on an address trace T ...
The cache Miss Ratio Curve (MRC) serves a variety of purposes such as cache partitioning, applicatio...
In this paper, we use execution-driven simulation to study and compare vector processing performance...
Detailed micro-architecture studies often require time-consuming, cycle-accurate simulation. Unfortu...
With the software applications increasing in complexity, description of hardware is becoming increas...
SPEC compute intensive benchmarks are often used to evaluate processors in high-performance systems....
Abstract—Although modeling of memory caches for the purpose of cache design and process scheduling h...
Measurements of actual supercomputer cache performance has not been previously undertaken. PFC-Sim i...
Abstract-Design parameters interact in complex ways in modern processors, especially because out-of-...
Memory performance can be studied, process behavior can be characterized, and application performanc...
The floating point portion of the SPEC CPU suite and the HPC Challenge suite are widely recognized a...
AbstractThe embedded processor performance is significantly influenced by cache whose performance de...
This report presents results of the experiments assessing the sensitivity of SPEC CPU2006 benchmarks...
A new performance model of the memory hierarchy is first introduced, which describes all possible sc...
SIGLEAvailable at INIST (FR), Document Supply Service, under shelf-number : 14802 E, issue : a.1990 ...
The standard trace-driven cache simulation evaluates the miss rate of cache C on an address trace T ...
The cache Miss Ratio Curve (MRC) serves a variety of purposes such as cache partitioning, applicatio...
In this paper, we use execution-driven simulation to study and compare vector processing performance...