A modeling approach and design tool for pipelined central processors

As CPUs have become larger and more complex, it has become increasingly more difficult during hardware design and implementation to predict how well a CPU will perform. Furthermore, buyers of such machines have a similar problem in evaluating CPU performance among a diverse selection of computers, since MIP rates quoted by manufacturers may be misleading. This paper describes a methodology based on simulation models for predicting the performance of central processors with instruction execution that occurs in distinct and separable phases. The basic components of the model have been designed to allow a functional representation of the instruction execution path. This provides a natural mapping of the instruction set onto the architecture in a manner familiar to the designer. The model has been verified for existing computers using actual trace data from these machines. Novel aspects of the model and its use in CPU design are discussed