In this paper we describe the VLSI design and testing of a high capacity associative memory which we call the exponential correlation associative memory (ECAM). The prototype 3µ-CMOS programmable chip is capable of storing 32 memory patterns of 24 bits each. The high capacity of the ECAM is partly due to the use of special exponentiation neurons, which are implemented via sub-threshold MOS transistors in this design. The prototype chip is capable of performing one associative recall in 3 µS
Rückert U, Goser K. VLSI-Architectures for Associative Networks. In: Proceedings of the IEEE Intern...
Rückert U, Kleerbaum C, Goser K. Digital VLSI Implementation of an Associative Memory Based on Neura...
Neural networks used as content-addressable memories show unequaled retrieval and speed capabilities...
In this paper we describe the VLSI design and testing of a high capacity associative memory which w...
In this paper we describe the VLSI design and testing of a high capacity associative memory which we...
A model for a class of high-capacity associative memories is presented. Since they are based on two-...
A generalized associative memory model with potentially high capacity is presented. A memory of this...
Rückert U. An Associative Memory with Neural Architecture and its VLSI Implementation. In: Milutinov...
Rückert U. VLSI Implementation of an Associative Memory Based on Distributed Storage of Information....
A large scale collective system implementing a specific model for associative memory was described b...
Rückert U, Rüping S, Naroska E. Parallel Implementation of Neural Associative Memories on RISC Proce...
Re-awaking in the 1980s from a rather chequered history Artificial Neural Networks (ANNs) have susta...
Neurocomputers offer a massively parallel computing paradigm by mimicking the human brain. Their eff...
International audienceThis paper addresses the definition of the requirements for the design of a ne...
Abstrud-Hopfield’s neural networks show retrieval and speed capabili-ties that make them good candid...
Rückert U, Goser K. VLSI-Architectures for Associative Networks. In: Proceedings of the IEEE Intern...
Rückert U, Kleerbaum C, Goser K. Digital VLSI Implementation of an Associative Memory Based on Neura...
Neural networks used as content-addressable memories show unequaled retrieval and speed capabilities...
In this paper we describe the VLSI design and testing of a high capacity associative memory which w...
In this paper we describe the VLSI design and testing of a high capacity associative memory which we...
A model for a class of high-capacity associative memories is presented. Since they are based on two-...
A generalized associative memory model with potentially high capacity is presented. A memory of this...
Rückert U. An Associative Memory with Neural Architecture and its VLSI Implementation. In: Milutinov...
Rückert U. VLSI Implementation of an Associative Memory Based on Distributed Storage of Information....
A large scale collective system implementing a specific model for associative memory was described b...
Rückert U, Rüping S, Naroska E. Parallel Implementation of Neural Associative Memories on RISC Proce...
Re-awaking in the 1980s from a rather chequered history Artificial Neural Networks (ANNs) have susta...
Neurocomputers offer a massively parallel computing paradigm by mimicking the human brain. Their eff...
International audienceThis paper addresses the definition of the requirements for the design of a ne...
Abstrud-Hopfield’s neural networks show retrieval and speed capabili-ties that make them good candid...
Rückert U, Goser K. VLSI-Architectures for Associative Networks. In: Proceedings of the IEEE Intern...
Rückert U, Kleerbaum C, Goser K. Digital VLSI Implementation of an Associative Memory Based on Neura...
Neural networks used as content-addressable memories show unequaled retrieval and speed capabilities...