Add to ORKGA hierarchical timing simulation model has been developed to deal with VLSI designs at any level of representation. A set of physically based parameters are used to characterize the behavior and timing of a semantic design object (cell) independent of its composition environment. As cells are composed, the parameters of the composite cell can be determined from those of the component cells either analytically or by simulation. Based on this model, a behavior-level simulator has been developed and combined with other tools to form an integrated design system that fully supports the structured design methodology
Hardware simulation remains the most widely used technique for functional and timing verification an...
This paper describes the hierarchical design process for VLSI circuits and discusses the potential ...
We present a novel method to perform timing analysis of hierarchical circuits. It is based on the re...
A hierarchical timing simulation model has been developed to deal with VLSI designs at any level of...
A hierarchical timing simulation model for digital MOS circuits and systems is presented. This model...
The nature of hierarchical design tools for VLSI implementation is explored in terms of the "Caltec...
Simulation consists of exercising the representation of a design on a general purpose computer. It d...
We present a hierarchical methodology for ensuring functionally correct VLSI designs. This methodolo...
Due to the increasing complexity of VLSI systems and time-to-marketrequirements, efficient design me...
This thesis presents systematic modeling and analysis techniques for the accurate and efficient timi...
Simulation needs for design analysis, verification, and testing have become increasingly important a...
This paper presents model of hierarchical discrete-event simulation algorithm running on a hypercube...
A design representation that incorporates descriptions at more than one level of abstraction is call...
A new and efficient procedure is proposed to evaluate the timing performance of VLSI circuits with c...
245 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985.This dissertation deals with ...
Hardware simulation remains the most widely used technique for functional and timing verification an...
This paper describes the hierarchical design process for VLSI circuits and discusses the potential ...
We present a novel method to perform timing analysis of hierarchical circuits. It is based on the re...
A hierarchical timing simulation model has been developed to deal with VLSI designs at any level of...
A hierarchical timing simulation model for digital MOS circuits and systems is presented. This model...
The nature of hierarchical design tools for VLSI implementation is explored in terms of the "Caltec...
Simulation consists of exercising the representation of a design on a general purpose computer. It d...
We present a hierarchical methodology for ensuring functionally correct VLSI designs. This methodolo...
Due to the increasing complexity of VLSI systems and time-to-marketrequirements, efficient design me...
This thesis presents systematic modeling and analysis techniques for the accurate and efficient timi...
Simulation needs for design analysis, verification, and testing have become increasingly important a...
This paper presents model of hierarchical discrete-event simulation algorithm running on a hypercube...
A design representation that incorporates descriptions at more than one level of abstraction is call...
A new and efficient procedure is proposed to evaluate the timing performance of VLSI circuits with c...
245 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985.This dissertation deals with ...
Hardware simulation remains the most widely used technique for functional and timing verification an...
This paper describes the hierarchical design process for VLSI circuits and discusses the potential ...
We present a novel method to perform timing analysis of hierarchical circuits. It is based on the re...