Add to ORKGIn this paper we explore global and local properties of asynchronous circuits sized for the energy efficiency metric Et^2. We develop a theory that enables an abstract view on transistor sizing. These results allow us to accurately estimate circuit performance and compare circuit design choices at logic gate level without going through the costly sizing process. We estimate that the improvement in energy efficiency due to sizing is 2 to 3.5 times when compared to a design optimized for speed
This paper relates the potential energy savings to the energy profile of a circuit. These savings ar...
We initiate the theoretical investigation of energy-efficient circuit design. We assume that the cir...
Power consumption has become one of the most critical concerns for processor design. Parallelism of...
In this paper we explore global and local properties of asynchronous circuits sized for the energy e...
This paper studies the problem of transistor sizing of CMOS circuits optimized for energy-delay effi...
We investigate an efficiency metric for VLSI computation that includes energy, E, and time, t, in th...
This paper introduces an automated transistor sizing tool (ASAP) that incorporates accurate gateleve...
In this paper we introduce an energy-delay efficiency metric that captures any trade-off between the...
This paper studies the problem of transistor sizing of CMOS circuits optimized for energy-delay effi...
As complexity increases and gate sizes shrink for monolithic, mixed-signal integrated circuit (IC) t...
In this paper we address the problem of optimization of VLSI circuits to minimize power consumptioin...
This paper focuses on electronic design at circuit level. The use of evolutionary algorithms to this...
We initiate the theoretical investigation of energy-efficient circuit design.\ud We assume that the ...
ISBN 2-84813-040-7To increase the autonomy of embedded systems such as portable phones or computers,...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
This paper relates the potential energy savings to the energy profile of a circuit. These savings ar...
We initiate the theoretical investigation of energy-efficient circuit design. We assume that the cir...
Power consumption has become one of the most critical concerns for processor design. Parallelism of...
In this paper we explore global and local properties of asynchronous circuits sized for the energy e...
This paper studies the problem of transistor sizing of CMOS circuits optimized for energy-delay effi...
We investigate an efficiency metric for VLSI computation that includes energy, E, and time, t, in th...
This paper introduces an automated transistor sizing tool (ASAP) that incorporates accurate gateleve...
In this paper we introduce an energy-delay efficiency metric that captures any trade-off between the...
This paper studies the problem of transistor sizing of CMOS circuits optimized for energy-delay effi...
As complexity increases and gate sizes shrink for monolithic, mixed-signal integrated circuit (IC) t...
In this paper we address the problem of optimization of VLSI circuits to minimize power consumptioin...
This paper focuses on electronic design at circuit level. The use of evolutionary algorithms to this...
We initiate the theoretical investigation of energy-efficient circuit design.\ud We assume that the ...
ISBN 2-84813-040-7To increase the autonomy of embedded systems such as portable phones or computers,...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
This paper relates the potential energy savings to the energy profile of a circuit. These savings ar...
We initiate the theoretical investigation of energy-efficient circuit design. We assume that the cir...
Power consumption has become one of the most critical concerns for processor design. Parallelism of...