Add to ORKGAn efficient baud rate clock and data recovery architecture is applied to a double sampling/integrating front-end receiver for optical interconnects. Receiver performance is analyzed and projected for future technologies. This front-end allows use of a 1:5 demux architecture to achieve 5Gb/s in a 0.25 μm CMOS process. A 5:1 multiplexing transmitter is used to drive VCSELs for optical transmission. The transceiver chip consumes 145mW per link at 5Gb/s with a 2.5V supply
A Bang-Bang Clock-Data Recovery (CDR) for 10Gb/s optical transmission systems is presented. A direct...
As computing systems and communication networks grow more complex, so is the need for higher bandwi...
This thesis presents the analysis, design, simulation, and measurements of a frequency detection met...
Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution...
A 1.6 Gb/s receiver for optical communication has been designed and fabricated in a 0.25-μm CMOS pro...
An optical interconnect transceiver incorporates a 4-tap FIR TX to reduce VCSEL average current and ...
Abstract—Interconnect architectures which leverage high-band-width optical channels offer a promisin...
This paper describes a dense, high-speed, and low-power CMOS optical receiver implemented in a 65-nm...
This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO...
The large demand for high-bandwidth communication systems has brought down the cost of optical syst...
Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a ...
This thesis presents an adaptive baud-rate CDR with CTLE and 1-tap DFE. The novelty in this design i...
This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channel...
This thesis discusses low-power wireline receivers with particular focus on clocking circuitry and ...
A new bit rate adaptive clock and data recovery circuit able to operate in a range from 3.125 Mb/s t...
A Bang-Bang Clock-Data Recovery (CDR) for 10Gb/s optical transmission systems is presented. A direct...
As computing systems and communication networks grow more complex, so is the need for higher bandwi...
This thesis presents the analysis, design, simulation, and measurements of a frequency detection met...
Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution...
A 1.6 Gb/s receiver for optical communication has been designed and fabricated in a 0.25-μm CMOS pro...
An optical interconnect transceiver incorporates a 4-tap FIR TX to reduce VCSEL average current and ...
Abstract—Interconnect architectures which leverage high-band-width optical channels offer a promisin...
This paper describes a dense, high-speed, and low-power CMOS optical receiver implemented in a 65-nm...
This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO...
The large demand for high-bandwidth communication systems has brought down the cost of optical syst...
Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a ...
This thesis presents an adaptive baud-rate CDR with CTLE and 1-tap DFE. The novelty in this design i...
This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channel...
This thesis discusses low-power wireline receivers with particular focus on clocking circuitry and ...
A new bit rate adaptive clock and data recovery circuit able to operate in a range from 3.125 Mb/s t...
A Bang-Bang Clock-Data Recovery (CDR) for 10Gb/s optical transmission systems is presented. A direct...
As computing systems and communication networks grow more complex, so is the need for higher bandwi...
This thesis presents the analysis, design, simulation, and measurements of a frequency detection met...