An Efficient Area and Low Power FIR Digital Filter Structure Implemented By Fast FIR Algorithm Utilizes the Symmetric Convolution

In Recent days the Finite Impulse Response FIR filter occupies the most important role in the digital system. In this paper explains the number of reduced multiplier increases with the length of the FIR filter structure designed by using the FIR algorithm, the number of reduced multiplier increases with the length of FIR filter structure it significant to the hardware for symmetric convolution from existing FFA parallel to the FIR filters and FIR filter designed by using the FIR algorithm. In this FIR filter structure using poly phase decomposition technique and it can requires minimum number of multipliers and it consumes for low power. Normally the multiplier consumes more power larger than the adder, In compared to multiplier it requires the minimum hardware cost and less power compared to the existing parallel FIR filter structure