Modeling and analysis of timing behavior for CMOS circuits

Design closure in today\u27s advanced chip construction requires a delicate balance among various conflicting constraints. These constraints include meeting the timing, power, and area specification of the end product. In this dissertation, we propose several techniques for modeling and analysis of timing behavior in order to achieve better timing performance in VLSI design. A CMOS logic gate can have multiple transistor connection structures while maintaining the same logic function. Since those different transistor connection structures represent different electrical circuits, their timing behaviors, especially propagation delays, will also be different. Transistor reordering is a technique to optimize the timing performance of a CMOS gate by determining good transistor connection structures. Transistor reordering is effective in reducing delays of a circuit with nearly zero penalties. However, techniques to determine those good transistor orders have not been proposed in literature. Previous work on this has to resort to running SPICE simulations for various meaningful transistor orders and selecting a best one, which is extremely time-consuming. This dissertation proposes an efficient and accurate technique at switch level for determining best transistor orders without the need for running SPICE simulations. Effective propagation delay estimation for gates is crucial in many stages of VLSI design. For small circuits with finalized design details and parameters, SPICE simulations can provide near exact delay information. For the delay estimations of circuits at early design stages or very large circuits, SPICE simulations are not practical; for those cases, instead, switch-level delay estimation should be used. To facilitate the development of a switch-level delay estimation tool, three components are essential, including delay model for logic gates, delay model for interconnections, and delay model for transmission gates. Delay models for interconnections have been extensively studied, but the research results for modeling the delay of logic gates and transmission gates are far from sufficient to be used in CAD tools. The lack of simple and effective gate delay models has led many researchers to applying unfit models to estimate gate delays. In this dissertation, by embedding concepts of electronic theories into switch-level piecewise analysis, a simple and efficient delay model for CMOS gates of general types (such as NAND, NOR, dynamic gates, complex gates, and transmission gates) is proposed. The other contribution in this dissertation is the gate delay estimation with multiple-input switching (MIS) (where signal switching can occur at multiple inputs, each with a unique slope and arrival time). The timing information provided in standard cell libraries is usually for single-input switching (SIS). The switch level gate delay estimation with MIS has not been sufficiently addressed. In this dissertation, we propose an efficient and accurate technique for estimating MIS delay given SIS timing information (provide by all standard cell libraries). Unlike all previous work, the proposed MIS modeling technique does not require knowledge of process technology parameters, layout details (such as transistor sizes, wire sizes/areas, intrinsic capacitance, etc.), and the tedious steps of running a huge number of SPICE simulations to prepare the lookup tables. Thus, the proposed technique can fit into typical standard cell based design flow, where third-party libraries are used. In addition, the proposed MIS modeling technique is equally valid for working with gate delay models which provides SIS timing estimation. Numerous test cases over a wide range of process technologies (250, 130, and 50nm) have been experimented and compared with SPICE simulation results. (Abstract shortened by UMI.