As the CMOS technology nodes continue to shrink, the challenges of developing manufacturing tests for integrated circuits become more difficult to address. To detect parametric faults of new generation of integrated circuits such as 3D ICs, on-chip short-time intervals have to be accurately measured. The accuracy of an on-chip time measurement module is heavily affected by Process, supply Voltage, and Temperature (PVT) variations. This work presents a new on-chip time measurement scheme where the undesired effects of PVT variations are attenuated significantly. To overcome the effects of PVT variations on short-time measurement, phase locking methodology is utilized to implement a robust Vernier delay line. A prototype Time-to-Digital Conve...
This paper describes a programmable time measurement architecture that facilitates memory characteri...
Verification of timing performance in integrated circuits (ICs) is becoming more difficult as clock...
Over the past few decades, the advancement in the deep-submicron CMOS process technology has dramati...
As technology continues to shrink, the challenges of developing manufacturing tests for integrated c...
This paper presents a fine-coarse time interval measurement scheme which is resilient to the variati...
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Com...
In this dissertation, we propose an on-chip timing measurement technique. We design a TVC (time-to-v...
While on-chip delay measurement combining logic BIST with a variable test clock is an effective way ...
With the rapid advances in process technologies, the performance of state-of-the-art integrated circ...
Time-domain testing remains one of the most challenging obstacles for the semiconductor industry in ...
This thesis presents innovations for a special class of circuits called Time Difference (TD) circuit...
Reliability, power consumption and timing performance are key concerns for today's integrated circui...
Noise such as voltage drop and temperature in integrated circuits can cause significant performance ...
As technology node continues to shrink to achieve higher performance at high density, it has become ...
Increasing performance demands in advanced technology, together with limited energy budgets, force i...
This paper describes a programmable time measurement architecture that facilitates memory characteri...
Verification of timing performance in integrated circuits (ICs) is becoming more difficult as clock...
Over the past few decades, the advancement in the deep-submicron CMOS process technology has dramati...
As technology continues to shrink, the challenges of developing manufacturing tests for integrated c...
This paper presents a fine-coarse time interval measurement scheme which is resilient to the variati...
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Com...
In this dissertation, we propose an on-chip timing measurement technique. We design a TVC (time-to-v...
While on-chip delay measurement combining logic BIST with a variable test clock is an effective way ...
With the rapid advances in process technologies, the performance of state-of-the-art integrated circ...
Time-domain testing remains one of the most challenging obstacles for the semiconductor industry in ...
This thesis presents innovations for a special class of circuits called Time Difference (TD) circuit...
Reliability, power consumption and timing performance are key concerns for today's integrated circui...
Noise such as voltage drop and temperature in integrated circuits can cause significant performance ...
As technology node continues to shrink to achieve higher performance at high density, it has become ...
Increasing performance demands in advanced technology, together with limited energy budgets, force i...
This paper describes a programmable time measurement architecture that facilitates memory characteri...
Verification of timing performance in integrated circuits (ICs) is becoming more difficult as clock...
Over the past few decades, the advancement in the deep-submicron CMOS process technology has dramati...