Process Optimization for Carbon Nanotubes-On-Graphene Fabrication

Because of their superior thermal and electrical properties, carbon nanotubes (CNTs) and graphene (Gr) are promising candidates to replace copper and tungsten as interconnect materials in the most advanced integrated circuit technologies. We explore a three-dimensional all-carbon interconnect structure, consisting of vertically aligned CNTs grown directly on multi-layer graphene (MLG). The objective is to grow the CNTs with little or no damage to the graphene underlayer. We start with fabricating test structures using both plasma enhanced chemical vapor deposition (PECVD) and thermal CVD throughout the CNT growth process to confirm the results of previous work of our research group. We then proceed to design a process to grow CNTs using PECVD in order to achieve a test structure with not only vertically aligned CNTs, but also a conductive graphene underlayer. In order to achieve this, we vary the plasma conditions within the reactor during the CNT growth process and analyze the fabricated test structure using a scanning electron microscope (SEM) and a wafer probe station. Through our analysis we are able to determine the viability of our designed process. We are able to produce a test structure with partially aligned CNTs and an intact graphene underlayer by lowering the DC voltage of the plasma used in the PECVD process. As a result, we find that resistance of the sample is comparable to that of plain graphene. Three-dimensional all-carbon nanostructures such as the ones fabricated in our project can lead to functionalization of such structures as building blocks for future on-chip interconnects